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74VHC157MTCX

器件描述:Quad 2-Input Multiplexer
器件厂商:FAIRCHILD [Fairchild Semiconductor]
文件大小:70.72KB,共7页
Sponsor by e络盟
器件资料摘要:
November 1992
Revised April 1999
7
4
VH
C15
7
Quad
2-I
nput
Mult
ip
lexer
© 1999 Fairchild Semiconductor Corporation DS011536.prf www.fairchildsemi.com
74VHC157
Quad 2-Input Multiplexer
General Description
The VHC157 is an advanced high speed CMOS Quad 2-
Channel Multiplexer fabricated with silicon gate CMOS
technology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
It consists of four 2-input digital multiplexers with common
select and enable inputs. When the ENABLE input is held
“H” level, selection of data is inhibited and all the outputs
become “L” level. The SELECT decoding determines
whether the I
0x
or I
1x
inputs get routed to their correspond-
ing outputs.
An Input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and on two supply systems such as battery back up. This
circuit prevents device destruction due to mismatched sup-
ply and input voltages.
Features
a73 High Speed: t
PD
= 4.1 ns (typ) at V
CC
= 5V
a73 Low power dissipation: I
CC
= 4 µA (max.) at T
A
= 25°C
a73 High noise immunity: V
NIH
= V
NIL
= 28% V
CC
(min.)
a73 Power down protection is provided on all inputs
a73 Low noise: V
OLP
= 0.8V (max.)
a73 Pin and function compatible with 74HC157

Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74VHC157M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
74VHC157SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC157MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC157N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
I
0a
–I
0d
Source 0 Data Inputs
I
1a
–I
1d
Source 1 Data Inputs
E Enable Input
S Select Input
Z
a
–Z
d
Outputs