EEWorld首页 新闻 论坛 博客 白皮书 专题 电子电路 电子器件 单片机 嵌入式 模拟电路 DSP FPGA 电源管理 手机/便携 医疗电子 汽车电子 工业控制
厂商索引:A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U-V-W-X-Y-Z

74ABT16374CSSCX

器件描述:16-Bit D-Type Flip-Flop with 3-STATE Outputs
器件厂商:FAIRCHILD [Fairchild Semiconductor]
文件大小:86.82KB,共6页
Sponsor by e络盟
器件资料摘要:
© 2005 Fairchild Semiconductor Corporation DS011668 www.fairchildsemi.com
March 1994
Revised May 2005
7
4
AB
T1
6374
1
6
-Bi
t
D-T
ype Fli
p
-F
lop wit
h

3-
ST
A
T
E Output
s
74ABT16374
16-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ABT16374 contains sixteen non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP) and Output Enable (OE) are common to each byte
and can be shorted together for full 16-bit operation.
Features
a73 Separate control logic for each byte
a73 16-bit version of the ABT374
a73 Edge-triggered D-type inputs
a73 Buffered Positive edge-triggered clock
a73 High impedance glitch free bus loading during entire
power up and power down cycle
a73 Non-destructive hot insertion capability
a73 Guaranteed latch-up protection

Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagram
Order Number Package Number Package Description
74ABT16374CSSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74ABT16374CMTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Name Description
OE
n
3-STATE Output Enable Input (Active LOW)
CP
n
Clock Pulse Input (Active Rising Edge)
D
0
–D
15
Data Inputs
O
0
–O
15
3-STATE Outputs