ASMP5P23S09A
August 2004 ASMP5P23S05A
rev 2.0
Alliance Semiconductor
2575, Augustine Drive ÿ Santa Clara, CA ÿ Tel: 408.855.4900 ÿ Fax: 408.855.4999 ÿ www.alsc.com
Notice: The information in this document is subject to change without notice.
PLL CLKOUT
CLK1
CLK2
CLK3
CLK4
REF
ASM5P23S05A
3.3V ÿSpreadTrakþ Zero Delay Buffer
General Features
ÿ 10 MHz to 133- MHz operating range, compatible
with CPU and PCI bus frequencies.
ÿ Zero input - output propagation delay.
ÿ Multiple low-skew outputs.
ÿ Output-output skew less than 250 ps.
ÿ Device-device skew less than 700 ps.
ÿ One input drives 9 outputs, grouped as 4 + 4
+ 1 (ASM5P23S09A).
ÿ One input drives 5 outputs (ASM5P23S05A).
ÿ Less than 200 ps cycle-to-cycle jitter is compatible
with Pentium® based systems.
ÿ Test Mode to bypass PLL (ASM5P23S09A only,
refer Select Input Decoding Table).
ÿ Available in 16-pin, 150-mil SOIC, 4.4 mm
TSSOP, and 150-mil SSOP packages
(ASM5P23S09A) or in 8-pin, 150-mil SOIC
package (ASM5P23S05A).
ÿ 3.3V operation, advanced 0.35µ CMOS
technology.
ÿ ÿSpreadTrakþ.
Functional Description
ASM5P23S09A is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed clocks with Spread
Spectrum capability. It is available in a 16-pin package. The
ASM5P23S05A is the eight-pin version of the
ASM5P23S09A. It accepts one reference input and drives
out five low-skew clocks.
The -1H version of the ASM5P23SXXA operates at up to
133- MHz frequencies, and has higher drive than the -1
devices. All parts have on-chip PLLs that lock to an input
clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad.
The ASM5P23S09A has two banks of four outputs each,
which can be controlled by the Select inputs as shown in
the Select Input Decoding Table. If all the output clocks are
not required, Bank B can be three-stated. The select input
also allows the input clock to be directly applied to the
outputs for chip and system testing purposes.
Multiple ASM5P23S09A and ASM5P23S05A devices can
accept the same input clock and distribute it. In this case
the skew between the outputs of the two devices is
guaranteed to be less than 700ps.
All outputs have less than 200 ps of cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to be
less than 250 ps, and the output to output skew is
guaranteed to be less than 250ps.
The ASM5P23S09A and the ASM5P23S05A are available
in two different configurations, as shown in the ordering
information table. The ASM5P23SXXA-1 is the base part.
The ASM5P23SXXA-1H is the high drive version of the -1
and its rise and fall times are much faster than -1 part.
Block Diagram
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
CLKOUT
REF
S1
S2
Select Input
MUX
ASM5P23S09A
Decoding
PLL