))))/
# $65<)343
0
0 150 ns
DQ1 DQ2
V
DQ3 DQ4 DQ5 DQ6
32-pin
• High speed 120/150 ns address access time
• Low power consumption:
- 30 mA maximum read current
Low V
CC
detector
Program/erase
pulse timer
Y-GatingY-Decoder
c
h
6HOHFWLRQ#JXLGH
AS29
Maximum access time t
AA
12
Chip enable access time t
CE
12
A
0
~A
16
X-Decoder
1,048,576 bit
Cell matrix
Addr
es
s
la
t
','#4407333:0$1#72:233 $//,$1&(#6(0
Output enable access time t
OE
50
///$
$$$6
666+
+++
F010-120 AS29F010-150 Unit
150 ns
V
CC
WE
NC
A14
A13
A8
A9
A11 OE
A10
CE
DQ7
DQ6
DQ5
NC
A16
A15
A12
A7
A6
A5
A4 A3
A2
A1
A0
DQ0
DQ1
DQ2
V
SS
DQ4
DQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
31
30
29
28
27
26
25
24
23
22
21
20
19
15
16
18
17
TSOP
AS29F010
- 50 mA maximum program current
- 1.5 mA maximum standby current
- 1 mA maximum standby current (low power)
• 10,000 write/erase cycle endurance
/RJLF#EORFN#GLDJUDP
WE
CE
OE
State
control
Command
register
Erase voltage
switch
Input/output
buffers
Program voltage
switch
Data
latch
Chip enable
Output enable
Logic
DQ
0
~DQ
7
V
CC
V
SS
3LQ#DUUDQJHPHQW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE
NC*
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
V
SS
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
14 15
SS
16 17 18 19 20
4A
1
2
3A
1
5
2A
1
6
1N
C
32
V
CC
31
WE
30
NC
*
A0 12
DQ0 13
22 CE
21 DQ7
32-pin32-pin
PDIP PLCC
AS29F010
AS2
9F01
0
-Data polling
- DQ6 toggle
• Low V
CC
write lock-out below 3.2V
• JEDEC standard packages and pinouts:
-32-pin DIP
- 32-pin PLCC
- 32-pin TSOP
®
89#45;.ð;#&026#)ODVK#((3520
)HDWXUHV
• Organization: 128K × 8 bits
• Sector Erase architecture
- Four 32K × 8 sectors
• Single 5.0±0.5V power supply for read/write operations
• JEDEC standard write cycle commands
- protects data from accidental changes
• Program/erase cycle end signals:
Copyright ©1998 Alliance Semiconductor. All rights reserved.
,&21'8&725 4
50 ns