74VHC74
器件描述:Dual D-Type Flip-Flop with Set and Reset
文件大小:153.5KB,共6页
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器件资料摘要:
C0077C0079C0084C0079C0082C0079C0076C0065
SEMICONDUCTOR TECHNICAL DATA
1 REV 1 Motorola, Inc. 1997
6/97
C0068C0117C0097C0108 C0068C0045C0084C0121C0112C0101 C0070C0108C0105C0112C0045C0070C0108C0111C0112
C0119C0105C0116C0104 C0083C0101C0116 C0097C0110C0100 C0082C0101C0115C0101C0116
The MC74VHC74 is an advanced high speed CMOS D–type flip–flop
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The signal level applied to the D input is transferred to Q output during the
positive going transition of the Clock pulse.
Reset (RD) and Set (SD) are independent of the Clock (CP) and are
accomplished by setting the appropriate input Low.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
• High Speed: f
max
= 170MHz (Typ) at V
CC
= 5V
• Low Power Dissipation: I
CC
= 2µA (Max) at T
A
= 25°C
• High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: V
OLP
= 0.8V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 128 FETs or 32 Equivalent Gates
LOGIC DIAGRAM
RD1
D1
CP1
SD1
RD2
D2
CP2
SD2
1
2
3
4
13
12
11
10
5
6
9
8
Q1
Q1
Q2
Q2
FUNCTION TABLE
Inputs Outputs
SD RD CP D Q Q
LH XX HL
HL XX LH
L L X X H* H*
HH H HL
HH L LH
H H L X No Change
H H H X No Change
H H X No Change
* Both outputs will remain high as long as Set and Reset are low, but the output
states are unpredictable if Set and Reset go high simultaneously.
C0077C0067C0055C0052C0086C0072C0067C0055C0052
PIN ASSIGNMENT
SD1
CP1
D1
RD1
11
12
13
14
8
9
105
4
3
2
1
7
6
SD2
CP2
D2
RD2
V
CC
Q2
Q2
GND
Q1
Q1
D SUFFIX
14–LEAD SOIC PACKAGE
CASE 751A–03
DT SUFFIX
14–LEAD TSSOP PACKAGE
CASE 948G–01
ORDERING INFORMATION
MC74VHCXXD
MC74VHCXXDT
MC74VHCXXM
SOIC
TSSOP
SOIC EIAJ
M SUFFIX
14–LEAD SOIC EIAJ PACKAGE
CASE 965–01