74VHC138
器件资料摘要：
C0077C0079C0084C0079C0082C0079C0076C0065
SEMICONDUCTOR TECHNICAL DATA
1 REV 1 Motorola, Inc. 1997
6/97
C0051C0045C0116C0111C0045C0056 C0076C0105C0110C0101 C0068C0101C0099C0111C0100C0101C0114
The MC74VHC138 is an advanced high speed CMOS 3–to–8 decoder
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
When the device is enabled, three Binary Select inputs (A0 – A2)
determine which one of the outputs (Y0 – Y7) will go Low. When enable input
E3 is held Low or either E2 or E1 is held High, decoding function is inhibited
and all outputs go high. E3, E2, and E1 inputs are provided to ease cascade
connection and for use as an address decoder for memory systems.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
• High Speed: t
PD
= 5.7ns (Typ) at V
CC
= 5V
• Low Power Dissipation: I
CC
= 4µA (Max) at T
A
= 25°C
• High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: V
OLP
= 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 122 FETs or 30.5 Equivalent Gates
7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
9
10
11
12
13
14
15
3
2
1
E3
E2
A0
A1
A2
ACTIVE–LOW
OUTPUTS
SELECT
INPUTS
E1
ENABLE
INPUTS
4
5
6
Inputs Outputs
E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X X H XXXHHHHHHHH
X H X XXXHHHHHHHH
L X X XXXHHHHHHHH
H L L LLL LHHHHHHH
H L L LLHHLHHHHHH
H L L LHLHHLHHHHH
H L L LHHHHHLHHHH
H L L HLLHHHHLHHH
H L L HLHHHHHHLHH
H L L HHLHHHHHHLH
H L L HHHHHHHHHHL
FUNCTION TABLE
H = high level (steady state); L = low level (steady state);
X = don’t care
LOGIC DIAGRAM
C0077C0067C0055C0052C0086C0072C0067C0049C0051C0056
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
A0
E1
A2
A1
Y7
E3
E2
GND
Y3
Y2
Y1
Y0
V
CC
Y5
Y4
Y6
D SUFFIX
16–LEAD SOIC PACKAGE
CASE 751B–05
DT SUFFIX
16–LEAD TSSOP PACKAGE
CASE 948F–01
ORDERING INFORMATION
MC74VHCXXXD
MC74VHCXXXDT
MC74VHCXXXM
SOIC
TSSOP
SOIC EIAJ
M SUFFIX
16–LEAD SOIC EIAJ PACKAGE
CASE 966–01
SEMICONDUCTOR TECHNICAL DATA
1 REV 1 Motorola, Inc. 1997
6/97
C0051C0045C0116C0111C0045C0056 C0076C0105C0110C0101 C0068C0101C0099C0111C0100C0101C0114
The MC74VHC138 is an advanced high speed CMOS 3–to–8 decoder
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
When the device is enabled, three Binary Select inputs (A0 – A2)
determine which one of the outputs (Y0 – Y7) will go Low. When enable input
E3 is held Low or either E2 or E1 is held High, decoding function is inhibited
and all outputs go high. E3, E2, and E1 inputs are provided to ease cascade
connection and for use as an address decoder for memory systems.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
• High Speed: t
PD
= 5.7ns (Typ) at V
CC
= 5V
• Low Power Dissipation: I
CC
= 4µA (Max) at T
A
= 25°C
• High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: V
OLP
= 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 122 FETs or 30.5 Equivalent Gates
7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
9
10
11
12
13
14
15
3
2
1
E3
E2
A0
A1
A2
ACTIVE–LOW
OUTPUTS
SELECT
INPUTS
E1
ENABLE
INPUTS
4
5
6
Inputs Outputs
E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X X H XXXHHHHHHHH
X H X XXXHHHHHHHH
L X X XXXHHHHHHHH
H L L LLL LHHHHHHH
H L L LLHHLHHHHHH
H L L LHLHHLHHHHH
H L L LHHHHHLHHHH
H L L HLLHHHHLHHH
H L L HLHHHHHHLHH
H L L HHLHHHHHHLH
H L L HHHHHHHHHHL
FUNCTION TABLE
H = high level (steady state); L = low level (steady state);
X = don’t care
LOGIC DIAGRAM
C0077C0067C0055C0052C0086C0072C0067C0049C0051C0056
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
A0
E1
A2
A1
Y7
E3
E2
GND
Y3
Y2
Y1
Y0
V
CC
Y5
Y4
Y6
D SUFFIX
16–LEAD SOIC PACKAGE
CASE 751B–05
DT SUFFIX
16–LEAD TSSOP PACKAGE
CASE 948F–01
ORDERING INFORMATION
MC74VHCXXXD
MC74VHCXXXDT
MC74VHCXXXM
SOIC
TSSOP
SOIC EIAJ
M SUFFIX
16–LEAD SOIC EIAJ PACKAGE
CASE 966–01