© 2001 Fairchild Semiconductor Corporation DS011359 www.fairchildsemi.com
February 1992
Revised June 2001
7
4
L
V
Q373 Low
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Out
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74LVQ373
Low Voltage Octal Transparent Latch
with 3-STATE Outputs
General Description
The LVQ373 consists of eight latches with 3-STATE out-
puts for bus organized system applications. The latches
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is low, the data satisfying the input timing
requirements is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state.
Features
a73 Ideal for low power/low noise 3.3V applications
a73 Implements patented EMI reduction circuitry
a73 Available in SOIC JEDEC, SOIC EIAJ and QSOP
packages
a73 Guaranteed simultaneous switching noise level and
dynamic threshold performance
a73 Improved latch-up immunity
a73 Guaranteed incident wave switching into 75Ω
a73 4 kV minimum ESD immunity

Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Pin Descriptions
Connection Diagram
Truth Table
H = HIGH Voltage Level L = LOW Voltage Level
Z = High Impedance X = Immaterial
O
0
= Previous O
0
before HIGH to Low transition of Latch Enable
Order Number Package Number Package Description
74LVQ373SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVQ373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVQ373QSC MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
Pin Names Description
D
0
–D
7
Data Inputs
LE Latch Enable Input
OE Output Enable Input
O
0
–O
7
3-STATE Latch Outputs
Inputs Outputs
LE OE D
n
O
n
XHX Z
HLL L
H H
LLX O
0