Order Number: 306666, Revision: 001
April 2005
Intel StrataFlash
®
Embedded Memory
(P30)
1-Gbit P30 Family
Datasheet
Product Features
The Intel StrataFlash
®
Embedded Memory (P30) product is the latest generation of Intel
StrataFlash
®
memory devices. Offered in 64-Mbit up through 1-Gbit densities, the P30 device
brings reliable, two-bit-per-cell storage technology to the embedded flash market segment.
Benefits include more density in less space, high-speed interface, lowest cost-per-bit NOR
device, and support for code and data storage. Features include high-performance synchronous-
burst read mode, fast asynchronous access times, low power, flexible security options, and three
industry standard package choices.
The P30 product family is manufactured using Intel
®
130 nm ETOX™ VIII process technology.
■ High performance
— 85/88 ns initial access
— 40 MHz with zero wait states, 20 ns clock-to-
data output synchronous-burst read mode
— 25 ns asynchronous-page read mode
— 4-, 8-, 16-, and continuous-word burst mode
— Buffered Enhanced Factory Programming
(BEFP) at 5 µs/byte (Typ)
— 1.8 V buffered programming at 7 µs/byte (Typ)
■ Architecture
— Multi-Level Cell Technology: Highest Density
at Lowest Cost
— Asymmetrically-blocked architecture
— Four 32-KByte parameter blocks: top or
bottom configuration
— 128-KByte main blocks
■ Voltage and Power
—V
CC
(core) voltage: 1.7 V – 2.0 V
—V
CCQ
(I/O) voltage: 1.7 V – 3.6 V
— Standby current: 55 µA (Typ) for 256-Mbit
— 4-Word synchronous read current:
13 mA (Typ) at 40 MHz
■ Quality and Reliability
— Operating temperature: –40 °C to +85 °C
• 1-Gbit in SCSP is –30 °C to +85 °C
— Minimum 100,000 erase cycles per block
— ETOX™ VIII process technology (130 nm)
■ Security
— One-Time Programmable Registers:
• 64 unique factory device identifier bits
• 64 user-programmable OTP bits
• Additional 2048 user-programmable OTP bits
— Selectable OTP Space in Main Array:
• 4x32KB parameter blocks + 3x128KB main
blocks (top or bottom configuration)
— Absolute write protection: V
PP
= V
SS
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
■ Software
— 20 µs (Typ) program suspend
— 20 µs (Typ) erase suspend
—Intel
®
Flash Data Integrator optimized
— Basic Command Set and Extended Command
Set compatible
— Common Flash Interface capable
■ Density and Packaging
— 64/128/256-Mbit densities in 56-Lead TSOP
package
— 64/128/256/512-Mbit densities in 64-Ball
Intel® Easy BGA package
— 64/128/256/512-Mbit and 1-Gbit densities in
Intel® QUAD+ SCSP
— 16-bit wide data bus