March 2004
AS7C513B
OE 20 A9A12 25
10 10 10 mA
CE
LB
Selection guide
-10
Maximum address access time 10
Maximum output enable access time 56
Maximum operating current 110
Maximum CMOS standby current 10
3/26/04, v.1.3 Alliance Semiconductor
A10
NC
21
22
A11
NC
24
23
-12 -15 -20 Unit
12 15 20 ns
78
100 90 80 mA
• Low power consumption: STANDBY
• 55 mW / max CMOS I/O
• 6T 0.18u CMOS Technology
Logic block diagram
32K × 16
Array
WE
Column decoder
Row decoder
A0
A1
A2
A3
A4
A5
A7
V
CC
GND
A8 A9
A10 A1
1
A12 A13 A14
Control circuit
I/O0–I/O7
I/O8–I/O15
UB
I/O
buffer
A6
Pin arrangement
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
I/O13
I/O12
GND
V
CC
I/O11
I/O10
I/O9
I/O8
NC
A7
A8
A0
CE
I/O0
I/O1
I/O2
I/O3
V
CC
GND
I/O4
I/O5
I/O6
I/O7
WE
A14
A13
44-Pin SOJ, TSOP 2 (400 mil)
UB
LB
I/O15
I/O14
2A3
3A2
4A1
1NC
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
43
42
41
44
A5
A6
OE
A4
AS7C513
B
®
5V 32K×16 CMOS SRAM
Features
• Industrial and commercial temperature
• Organization: 32,768 words × 16 bits
• Center power and ground pins
•High speed
• 10/12/15/20 ns address access time
• 5, 6, 7, 8 ns output enable access time
• Low power consumption: ACTIVE
• 605mW / max @ 10 ns
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• 44-pin JEDEC standard package
•400 mil SOJ
• 400 mil TSOP 2
• ESD protection > 2000 volts
• Latch-up current > 200 mA
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