May 2002
AS7C1024A
145 140 mA
Sense amp
A1
0
A1
1
A1
2
A1
3
A1
4
A1
5
A1
6
I/O0
OE
CE1
WE
Column decoder
Ro
Control
circuit
A9
A6
A7
A8
CE2
Selection guide
-10 -1
Maximum address access time 10 12
Maximum output enable access time 5 6
Maximum
AS7C1024A 155 150
9/26/02; 0.9.9 Alliance Semiconductor
operating current
AS7C31024A 145
Maximum CMOS
standby current
AS7C1024A 10
AS7C31024A 5
V
CC
A15
CE2
WE
A13 I/O7
I/O6
I/O4
NC
A16
A14
A12
A7
A6
A5
A4 A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
I/O5
I/O3
4
5
6
7
8
9
10
11
12
13
14
29
28
27
26
25
24
23
22
21
AS7C1024A
AS7C31024A
20
19
15
16
18
17
2 -15 -20 Unit
15 20 ns
7 8 ns
High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
Low power consumption: ACTIVE
- 853 mW (AS7C1024A) / max @ 10 ns
- 522 mW (AS7C31024A) / max @ 10 ns
Low power consumption: STANDBY
- 55 mW (AS7C1024A) / max CMOS
- 36 mW (AS7C31024A) / max CMOS
Logic block diagram
512×256×8
Array
(1,048,576)
Input buffer
I/O7
w decoder
A0
A1
A2
A3
A4
A5
V
CC
GND
P
- 400 mil SOJ
-8 × 20mm TSOP 1
- 8 x 13.4mm sTSOP 1
ESD protection ≥ 2000 volts
Latch-up current ≥ 200 mA
in arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
AS7C
10
24A
AS7C
31
024A
32-pin SOJ (300 mil)
A8
A9
A11 OE
A10
CE1

1
2
3
32
31
30
32-pin (8 x 20mm) TSOP I
32-pin SOJ (400 mil)
32-pin (8 x 13.4mm) sTSOP1
®
AS7C31024A
5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout)
Features
• AS7C1024A (5V version)
AS7C31024A (3.3V version)
Industrial and commercial temperatures
Organization: 131,072 words x 8 bits
Latest 6T 0.25u CMOS technology
Easy memory expansion with CE1, CE2, OE inputs
TTL/LVTTL-compatible, three-state I/O
32-pin JEDEC standard packages
- 300 mil SOJ
Copyright © Alliance Semiconductor. All rights reserved.
P. 1 of 9
140 135 130 mA
10 10 10 mA
5 5 5 mA