January 2005
AS7C4096
• Low power consumption: ACTIVE
CE
Circuit
19 NC18A9
NC
A10A8
A9
26
25
19
20
– 20 20 20 mA
A10 A1
1
A12 A13 A14 A15 A16 A17 A18
Selection guide
Maximum address access time
Maximum outputenable access time
Maximum operating current
AS7C4096
AS7C34096
Maximum CMOS standby current
AS7C4096
1/13/05; v.1.9 Alliance Semico
AS7C34096
24
23
21
22
NC
NC
NC
NC
–10 –12 –15 –20 Unit
10 12 15 20 ns
5 6 7 8 ns
– 250 220 180 mA
160 130 110 100 mA
- 1375 mW (AS7C4096) / max @ 12 ns
- 576 mW (AS7C34096) / max @ 10 ns
• ESD pr
• L
Logic block diagram
524,288 × 8
Array
(4,194,304)
S
e
ns
e am
p
Input buffer
I/O8
I/O1
OE
WEColumn decoder
Row decoder
Control
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
A8
A9
Pin arran
- 400 mil 36-pin SOJ
- 44-pin TSOP 2
otection ≥ 2000 volts
atch-up current ≥ 100 mA
gements
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
A15
OE
I/O8
I/O7
GND
V
CC
I/O6
I/O5
A14
A13
A12
A11
A10
A0
A1
A2
A3
A4
CE
I/O1
I/O2
V
CC
GND
I/O3
I/O4
WE
A5
A6
A7
17A8
36
35
34
33
NC
A18
A17
A16
GND
V
CC
I/O6
I/O5
A14
A13
A12
A11
A4
CE
I/O1
I/O2
V
CC
GND
I/O3
I/O4
WE
A5
A6
A7
I/O8
I/O7
A1
A2
A3
A0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
43
42
41
44
A16
A15
A175
6
7
8
9
10
11
12
13
14
15
16
17
18
2
3
4
1
NC
NC
NC
NC
NC
OE
A18
36-pin SOJ (400 mil) 44-pin TSOP 2
AS7C34096
5V/3.3V 512K × 8 CMOS SRAM
®
Features
• AS7C4096 (5V version)
• AS7C34096 (3.3V version)
• Industrial and commercial temperature
• Organization: 524,288 words × 8 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
• Low power consumption: STANDBY
- 110 mW (AS7C4096) / max CMOS
- 72 mW (AS7C34096) / max CMOS
• Equal access and cycle times
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packages
Copyright © Alliance Semiconductor. All rights reserved.
nductor P. 1 of 9
20 20 20 20 mA