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9240LPRPQI

器件描述:14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC
器件厂商:MAXWELL [Maxwell Technologies]
文件大小:495.23KB,共18页
Sponsor by e络盟
器件资料摘要:
1
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All data sheets are subject to change without notice
(858) 503-3300- Fax: (858) 503-3301- www.maxwell.com
14-Bit, 10 MSPS Monolithic A/D
9240LP
©2005 Maxwell Technologies
All rights reserved.
01.10.05 REV 6
Converter with LPT ASIC
FEATURES:
•RAD-PAK® radiation-hardened against natural
space radiation
Low power dissipation: 295 mW
Single 5 V supply
Integral nonlinearity error: 2.5 LSB
Differential nonlinearity error: 0.6 LSB
Input referred noise: 0.36 LSB
Complete: On-chip sample-and-hold amplifier and voltage
reference
Signal-to-noise and distortion ration: 77.5 dB
Spurious-free dynamic range: 90 dB
Out-of-range indicator
Straight binary output data
Total dose hardened to 100 Krads (Si), dependent on orbit
and mission duration
Single Event Latchup (SEL) protected
DESCRIPTION:
Maxwell Technologies’ 9240LP is a 14-bit, analog-to-digital
converter that operates at a 10 MSPS rate. Manufactured with
a high speed CMOS process, this ADC contains an on-chip,
high performance, low noise, sample-and-hold amplifier and
programmable voltage reference.
The 9240LP offers single supply operation and dissipates only
295 mW with a 5 volt supply. This device provides no missing
codes and excellent temperature drift performance over the
full operating temperature range.
The 9240LP utilizes Maxwell’s LPT™ Latchup Protection
Circuit.Maxwell Technologies' patented RAD-PAK® packaging
technology incorporates radiation shielding in the microcircuit
package. It eliminates the need for box shielding while provid-
ing the required radiation shielding for a lifetime in orbit or
space mission. In a GEO orbit, RAD-PAK® provides protection
to 100 krad (Si) radiation dose tolerance. This product is avail-
able with screening up to Maxwell Technologies self-defined
Class K.
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 4
BIT 5
BIT 3NC
BIAS
CAPB
CAPT
NC
CML
LPTref
VinA
VinB
LPTDVDD
LPTAVDD
D
VSS
A
VSS
DV
D
D
AV
D
D
NC
DRV
DD
CLK
LP
TS
T
A
T
U
S
LP
TBI
T
NC
BIT
14
RE
FC
O
M
Vr
e
f
SEN
SE
NC A
VSS
AV
D
D
NC NC OTC BI
T
1
BI
T 2
9240LP
9240LP BLOCK DIAGRAM
DVDD
DRVDD
VINA
VINB
VREF
LPTVREF
LPTBIT
AVDD
LPTAVDD
LPTDVDD
LPTDRVDD
LPTVINA
LPTVINB
LPTVREF
LPTSTATUS
CROW BAR
AVDD
DVDD
DRVDD
VINA
VINB
VREF
CU
RRE
N
T
SE
N
S
E
9240 14 Bit A/D
D
a
ta
Outputs
C
ontr
o
l S
i
g
n
a
l
s