7C1041AV33-12
器件资料摘要：
PRELIMINARY
256K x 16 Static RAM
CY7C1041AV33/
GVT73256A16
Cypress Semiconductor Corporation • 3901 North First Street San Jose CA 95134 408-943-2600
June 15, 2000
33
Features
• Fast access times: 10, 12 ns
Fast OE access times: 5, 6, and 7 ns
Single +3.3V ±0.3V power supply
Fully static—no clock or timing strobes necessary
All inputs and outputs are TTL-compatible
Three state outputs
Center power and ground pins for greater noise
immunity
Easy memory expansion with CE and OE options
Automatic CE power-down
High-performance, low power consumption, CMOS
double-poly, double-metal process
Packaged in 44-pin, 400-mil SOJ and 44-pin, 400-mil
TSOP
Functional Description
The CY7C1049AV33\GVT73512A8 is organized as a 262,144
x 16 SRAM using a four-transistor memory cell with a high-per-
formance, silicon gate, low-power CMOS process. Cypress
SRAMs are fabricated using double-layer polysilicon, dou-
ble-layer metal technology.
This device offers center power and ground pins for improved
performance and noise immunity. Static design eliminates the
need for external clocks or timing strobes. For increased sys-
tem flexibility and eliminating bus contention problems, this de-
vice offers Chip Enable (CE), separate Byte Enable controls
(BLE and BHE) and Output Enable (OE) with this organization.
The device offers a low-power standby mode when chip is not
selected. This allows system designers to meet low standby
power requirements.
Functional Block Diagram
CE#
ADDRESS BUFFER
ROW DECODER
COLUMN DECODER
MEMORY ARRAY
512 ROWS X 256 X 16
COLUMNS
I/O CONTROL
WE#
OE#
DQ8
DQ1
POWER
DOWN
A16
A0
DQ16
DQ9
BHE#
BLE#
VCC
VSS
Top View
SOJ/TSOP II
WE
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
V
CC
A
5
A
6
A
7
A
8
A
0
A
1
OE
V
SS
A
17
DQ
16
A
2
CE
DQ
3
DQ
1
DQ
2
BHE
A
3
A
4
18
17
20
19
DQ
4
27
28
25
26
22
21
23
24
V
SS
A
16
A
15
BLE
V
CC
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
A
14
A
13
A
12
A
11
A
9
A
10
NC
DQ
5
DQ
6
DQ
7
DQ
8
Pin Configuration
Selection Guide
CY7C1049AV33-10/
GVT73512A8-10
CY7C1049AV33-12/
GVT73512A8-12
Maximum Access Time (ns) 10 12
Maximum Operating Current (mA) 240 210
Maximum CMOS Standby Current (mA) Com’l/Ind’l 10 10
Com’l L3. 3.
256K x 16 Static RAM
CY7C1041AV33/
GVT73256A16
Cypress Semiconductor Corporation • 3901 North First Street San Jose CA 95134 408-943-2600
June 15, 2000
33
Features
• Fast access times: 10, 12 ns
Fast OE access times: 5, 6, and 7 ns
Single +3.3V ±0.3V power supply
Fully static—no clock or timing strobes necessary
All inputs and outputs are TTL-compatible
Three state outputs
Center power and ground pins for greater noise
immunity
Easy memory expansion with CE and OE options
Automatic CE power-down
High-performance, low power consumption, CMOS
double-poly, double-metal process
Packaged in 44-pin, 400-mil SOJ and 44-pin, 400-mil
TSOP
Functional Description
The CY7C1049AV33\GVT73512A8 is organized as a 262,144
x 16 SRAM using a four-transistor memory cell with a high-per-
formance, silicon gate, low-power CMOS process. Cypress
SRAMs are fabricated using double-layer polysilicon, dou-
ble-layer metal technology.
This device offers center power and ground pins for improved
performance and noise immunity. Static design eliminates the
need for external clocks or timing strobes. For increased sys-
tem flexibility and eliminating bus contention problems, this de-
vice offers Chip Enable (CE), separate Byte Enable controls
(BLE and BHE) and Output Enable (OE) with this organization.
The device offers a low-power standby mode when chip is not
selected. This allows system designers to meet low standby
power requirements.
Functional Block Diagram
CE#
ADDRESS BUFFER
ROW DECODER
COLUMN DECODER
MEMORY ARRAY
512 ROWS X 256 X 16
COLUMNS
I/O CONTROL
WE#
OE#
DQ8
DQ1
POWER
DOWN
A16
A0
DQ16
DQ9
BHE#
BLE#
VCC
VSS
Top View
SOJ/TSOP II
WE
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
V
CC
A
5
A
6
A
7
A
8
A
0
A
1
OE
V
SS
A
17
DQ
16
A
2
CE
DQ
3
DQ
1
DQ
2
BHE
A
3
A
4
18
17
20
19
DQ
4
27
28
25
26
22
21
23
24
V
SS
A
16
A
15
BLE
V
CC
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
A
14
A
13
A
12
A
11
A
9
A
10
NC
DQ
5
DQ
6
DQ
7
DQ
8
Pin Configuration
Selection Guide
CY7C1049AV33-10/
GVT73512A8-10
CY7C1049AV33-12/
GVT73512A8-12
Maximum Access Time (ns) 10 12
Maximum Operating Current (mA) 240 210
Maximum CMOS Standby Current (mA) Com’l/Ind’l 10 10
Com’l L3. 3.