C0077C0079C0084C0079C0082C0079C0076C0065
SEMICONDUCTOR TECHNICAL DATA
1 REV 1 Motorola, Inc. 1997
6/97
C0079C0099C0116C0097C0108 C0068C0045C0084C0121C0112C0101 C0076C0097C0116C0099C0104
C0119C0105C0116C0104 C0051C0045C0083C0116C0097C0116C0101 C0079C0117C0116C0112C0117C0116
The MC74VHC373 is an advanced high speed CMOS octal latch with
3–state output fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
This 8–bit D–type latch is controlled by a latch enable input and an output
enable input. When the output enable input is high, the eight outputs are in a
high impedance state.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
• High Speed: t
PD
= 5.0ns (Typ) at V
CC
= 5V
• Low Power Dissipation: I
CC
= 4µA (Max) at T
A
= 25°C
• High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: V
OLP
= 0.9V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 186 FETs or 46.5 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0
D1
D2
D3
D4
D5
D6
D7
18
17
14
13
8
7
4
3
1
OE
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
16
15
12
9
6
5
2
NONINVERTING
OUTPUTS
11
LE
OE LE Q
L
L
L
H
H
H
L
X
H
L
No Change
Z
INPUTS OUTPUT
FUNCTION TABLE
D
H
L
X
X
C0077C0067C0055C0052C0086C0072C0067C0051C0055C0051
DW SUFFIX
20–LEAD SOIC PACKAGE
CASE 751D–04
ORDERING INFORMATION
MC74VHCXXXDW
MC74VHCXXXDT
MC74VHCXXXM
SOIC
TSSOP
SOIC EIAJ
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
PIN ASSIGNMENT
Q2
D1
D0
Q0
OE
GND
Q3
D3
D2
Q1 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q6
D6
D7
Q7
V
CC
LE
Q4
D4
D5
Q5
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01