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厂商索引:A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U-V-W-X-Y-Z

54HC245

器件描述:Octal Bus Transceiver
器件厂商:ONSEMI [ON Semiconductor]
厂商主页:http://www.onsemi.com
文件大小:175.42KB,共7页
Sponsor by e络盟
器件资料摘要:
C0077C0079C0084C0079C0082C0079C0076C0065
SEMICONDUCTOR TECHNICAL DATA
1 REV 1 Motorola, Inc. 1997
6/97
C0079C0099C0116C0097C0108 C0066C0117C0115 C0084C0114C0097C0110C0115C0099C0101C0105C0118C0101C0114
The MC74VHC245 is an advanced high speed CMOS octal bus
transceiver fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
It is intended for two–way asynchronous communication between data
buses. The direction of data transmission is determined by the level of the
DIR input. The output enable pin (OE) can be used to disable the device, so
that the buses are effectively isolated.
All inputs are equipped with protection circuits against static discharge.
• High Speed: t
PD
= 4.0ns (Typ) at V
CC
= 5V
• Low Power Dissipation: I
CC
= 4µA (Max) at T
A
= 25°C
• High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: V
OLP
= 1.2V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 308 FETs or 77 Equivalent Gates
APPLICATION NOTES
1. Do not force a signal on an I/O pin when it is an active output, damage may
occur.
2. All floating (high impedence) input or I/O pins must be fixed by means of
pull up or pull down resistors or bus terminator ICs.
3. A parasitic diode is formed between the bus and V
CC
terminals. Therefore,
the VHC245 cannot be used to interface 5V to 3V systems directly.
LOGIC DIAGRAM
A
DATA
PORT
A8
A7
A6
A5
A3
A4
A2
A1
9
8
7
6
5
4
3
2
DIR
OE
1
19
18
17
16
15
14
13
12
11
B1
B2
B3
B4
B5
B6
B7
B8
B
DATA
PORT
FUNCTION TABLE
Control Inputs
OiOE DIR Operation
L L Data Transmitted from Bus B to Bus A
L H Data Transmitted from Bus A to Bus B
H X Buses Isolated (High–Impedance State)
C0077C0067C0055C0052C0086C0072C0067C0050C0052C0053
PIN ASSIGNMENT
A5
A3
A2
A1
DIR
GND
A8
A7
A6
A4 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
B3
B2
B1
OE
V
CC
B8
B7
B6
B5
B4
DW SUFFIX
20–LEAD SOIC PACKAGE
CASE 751D–04
ORDERING INFORMATION
MC74VHCXXXDW
MC74VHCXXXDT
MC74VHCXXXM
SOIC
TSSOP
SOIC EIAJ
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01