PQFP
VQFP
TQFP
PBGA
FBGA
208
100
144, 176
—
144
208
100
176
—
—
208
100
144, 176
—
—
208
—
144, 176
313, 329
—
v3.1
54SX Family FPGAs
Leading Edge Performance
• 320 MHz Internal Performance
3.7 ns Clock-to-Out (Pin-to-Pin)
0.1 ns Input Set-Up
0.25 ns Clock Skew
Specifications
12,000 to 48,000 System Gates
Up to 249 User-Programmable I/O Pins
Up to 1080 Flip-Flops
0.35µ CMOS
Features
66 MHz PCI
CPLD and FPGA Integration
Single Chip Solution
100% Resource Utilization with 100% Pin Locking
3.3V Operation with 5.0V Input Tolerance
Very Low Power Consumption
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Debug capability with
Silicon Explorer II
Boundary Scan Testing in Compliance with IEEE Standard
1149.1 (JTAG)
Secure Programming Technology Prevents Reverse
Engineering and Design Theft
SX Product Profile
A54SX08 A54SX16 A54SX16P A54SX32
Capacity
Typical Gates
System Gates
8,000
12,000
16,000
24,000
16,000
24,000
32,000
48,000
Logic Modules
Combinatorial Cells
768
512
1,452
924
1,452
924
2,880
1800
Register Cells (Dedicated Flip-Flops) 256 528 528 1,080
Maximum User I/Os 130 175 175 249
Clocks 3333
JTAG YesYesYesYes
PCI —— s—
Clock-to-Out 3.7 ns 3.9 ns 4.4 ns 4.6 ns
Input Set-Up (External) 0.8 ns 0.5 ns 0.5 ns 0.1 ns
Speed Grades Std, –1, –2, –3 Std, –1, –2, –3 Std, –1, –2, –3 Std, –1, –2, –3
Temperature Grades C, I, M C, I, M C, I, M C, I, M
Packages (by pin count)
PLCC 84 — — —
June 2003 1
© 2003 Actel Corporation