© 2002 Fairchild Semiconductor Corporation DS005939 www.fairchildsemi.com
October 1987
Revised March 2002
CD400
1BC
/
CD401
1BC
Quad 2-
Input

NOR B
u
f
f
e
r
ed B
Ser
i
es Gate •
Quad 2-I
nput

NAND
Buf
f
er
ed B
Seri
es G
a
te
CD4001BC/CD4011BC
Quad 2-Input NOR Buffered B Series Gate
Quad 2-Input NAND Buffered B Series Gate
General Description
The CD4001BC and CD4011BC quad gates are monolithic
complementary MOS (CMOS) integrated circuits con-
structed with N- and P-channel enhancement mode tran-
sistors. They have equal source and sink current
capabilities and conform to standard B series output drive.
The devices also have buffered outputs which improve
transfer characteristics by providing very high gain.
All inputs are protected against static discharge with diodes
to V
DD
and V
SS
.
Features
a73 Low power TTL:
Fan out of 2 driving 74L compatibility: or 1 driving 74LS
a73 5V–10V–15V parametric ratings
a73 Symmetrical output characteristics
a73 Maximum input leakage 1 µA at 15V over full
temperature range

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC and SOP
CD4001BC
Top View
Pin Assignments for DIP and SOIC
CD4011BC
Top View
Order Number Package Number Package Description
CD4001BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4001BCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4001BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
CD4011BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4011BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide