3.3V, 160-MHz, 1:9 Clock Distribution Buffer
B9947
Cypress Semiconductor Corporation • 3901 North First Street San Jose CA 95134 408-943-2600
Document #: 38-07078 Rev. *C Revised December 22, 2002
Product Features
• 160-MHz Clock Support
LVCMOS/LVTTL Compatible Inputs
9 Clock Outputs: Drive up to 18 Clock Lines
Synchronous Output Enable
Output Three-state Control
350-ps Maximum Output-to-Output Skew
Pin Compatible with MPC947
Industrial Temp. Range: –40°C to +85°C
32-Pin TQFP Package
Description
The B9947 is a low-voltage clock distribution buffer with the
capability to select one of two LVCMOS/LVTTL compatible
clock inputs. The two clock sources can be used to provide for
a test clock as well as the primary system clock. All other con-
trol inputs are LVCMOS/LVTTL compatible. The nine outputs
are 3.3V LVCMOS or LVTTL compatible and can drive two
series terminated 50Ω transmission lines. With this capability
the B9947 has an effective fanout of 1:18. The outputs can
also be three-stated via the three-state input TS#. Low out-
put-to-output skews make the B9947 an ideal clock distribu-
tion buffer for nested clock trees in the most demanding of
synchronous systems.
The B9947 also provides a synchronous output enable input
for enabling or disabling the output clocks. Since this input is
internally synchronized to the input clock, potential output
glitching or runt pulse generation is eliminated.
B9947
VSS V
DDC
Q0 VSS Q1 V
DDC
Q2 VSS
VSS
V
DDC
Q8
VSS
Q7
V
DDC
Q6
VSS
VSS
Q3
VDDC
Q4
VSS
Q5
VDDC
VSS
VSS
TCLK_SEL
TCLK0
TCLK1
SYNC_OE
TS#
VDD
VSS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
Block Diagram Pin Configuration
0
1
TCLK1
TCLK_SEL
SYNC_OE
TS#
VDD VDDC
9
Q0-Q8
TCLK0