© 2005 Fairchild Semiconductor Corporation DS011616 www.fairchildsemi.com
June 1993
Revised April 2005
7
4
L
VX57
3

Low V
o
l
t
age Oct
a
l Lat
ch
wi
th 3-ST
A
T
E
Out
put
s
74LVX573
Low Voltage Octal Latch with 3-STATE Outputs
General Description
The LVX573 is a high-speed octal latch with buffered com-
mon Latch Enable (LE) and buffered common Output
Enable (OE) inputs. The LVX573 is functionally identical to
the LVX373 but with inputs and outputs on opposite sides
of the package. The inputs tolerate up to 7V allowing inter-
face of 5V systems to 3V systems.
Features
a73 Input voltage translation from 5V to 3V
a73 Ideal for low power/low noise 3.3V applications
a73 Guaranteed simultaneous switching noise level and
dynamic threshold performance

Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74LVX573M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVX573SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
D
0
–D
7
Data Inputs
LE Latch Enable Input
OE 3-STATE Output Enable Input
O
0
–O
7
3-STATE Latch Outputs