1
®
March 1997
82C284/883
Clock Generator and
Ready Interface for 80C286 Processors
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Generates System Clock for 80C286 Processors
• Generates System Reset Output from Schmitt Trigger
Input
- Improved Hysteresis
• Uses Crystal or External Signal for Frequency Source
- Dynamically Switchable Between Two Input
Frequencies
• Provides Local READY and MULTIBUS™ READY
Synchronization
• Static CMOS Technology
•Single +5V Power Supply
• Available in 18 Lead CERDIP Package
Pinout
82C284/883
(CERDIP)
TOP VIEW
Description
The Intersil 82C284/883 is a clock generator/driver which
provides clock signals for 80C286 processors and support
components. It also contains logic to supply READY to the
CPU from either asynchronous or synchronous sources and
synchronous RESET from an asynchronous input with hys-
teresis.
Functional Diagram
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1 VCC
S1
S0
NC
PCLK
RESET
RES
ARDYEN
CLK
ARDY
SRDY
SRDYEN
READY
EFI
F/C
X2
X1
GND
Ordering Information
PART NUMBER TEMP. RANGE PACKAGE PKG. NO.
MD82C284-12/883 -55
o
C to +125
o
C CERDIP F18.3
RESET
SYNCHRONIZER
RES
X1
X2
EFI
F/C
ARDYEN
ARDY
SRDYEN
SRDY
S1
S0
RESET
CLK
READY
PCLK
XTAL
OSC
MUX
SYNCHRONIZER
READY LOGIC
PCLK GENERATOR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
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