X T
April 1999
Intel and Pentium are registered trademarks of Intel Corporation. I
2
C is a licensed trademark of Philips Electronics, N.V. American Microsystems, Inc. reserves the right to change the detail specifica-
tions as may be required to permit improvements in the design of its products.
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1.0 Features
• Generates up to eighteen low-skew, non-inverting
clocks from one clock input
• Supports up to four SDRAM DIMMs
• Uses either I
2
C

-bus or SMBus serial interface with
Read and Write capability for individual clock output
control
• Output enable pin tristates all clock outputs to facili-
tate board testing
• Clock outputs skew-matched to less than 250ps
• Less than 5ns propagation delay
• Output impedance: 17W at 0.5V
DD
• Serial interface I/O meet I
2
C specifications; all other
I/O are LVTTL/LVCMOS-compatible
• Five differerent pin configurations available:
• FS6050: 18 clock outputs in a 48-pin SSOP
• FS6051: 10 clock outputs in a 28-pin SOIC, SSOP
• FS6053: 13 clock outputs in a 28-pin SOIC
• FS6054: 14 clock outputs in a 28-pin SOIC
Figure 1: Block Diagram (FS6050)
Serial
Interface
SDRAM_(0:1)
SCL
SDA
CLK_IN
OE
FS6050
SDRAM_(2:3)
SDRAM_(4:5)
SDRAM_(6:7)
SDRAM_(8:9)
SDRAM_(10:11)
SDRAM_(12:13)
SDRAM_(14:15)
SDRAM_16
VSS_I
2
C
VDD_I
2
C
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
SDRAM_17
VSS
VDD
18
2.0 Description
The FS6050 family of CMOS clock fanout buffer ICs are
designed for high-speed motherboard applications, such
as Intel Pentium
®
II PC100-based systems with 100MHz
SDRAM.
Up to eighteen buffered, non-inverting clock outputs are
fanned-out from one clock input. Individual clocks are
skew matched to less than 250ps at 100MHz. Multiple
power and ground supplies reduce the effects of supply
noise on device performance.
Under I
2
C-bus control, individual clock outputs may be
turned on or off. An active-low output enable is available
to force all the clock outputs to a tristate level for system
testing.
Figure 2: Pin Configuration (FS6050)
1
48
2 3 4 5 6 7 8
47 46 45 44 43 42 41
(
r
es
er
v
ed)
(
r
es
er
v
ed)
VD
D
S
DRA
M_
0
S
DRA
M_
1
VSS VD
D
S
DRA
M_
2
VS
S
SD
R
A
M
_14
SD
R
A
M
_15
(
r
es
er
v
e
d)
VD
D
(
r
es
er
v
e
d)
9
10 11 12 13 14 15 16
S
DRA
M_
3
VSS
CL
K
_
I
N
VD
D
S
DRA
M_
4
S
DRA
M_
5
VSS VD
D
17 18 19 20 21 22 23
S
DRA
M_
6
S
DRA
M_
7
VSS VD
D
S
DRA
M_
1
6
VSS
V
DD_
I
2
C
40 39 38 37 36 35 34 33
SD
R
A
M
_10
SD
R
A
M
_11
VD
D
OESD
R
A
M
_13
SD
R
A
M
_12
VS
S
VD
D
32 31 30 29 28 27 26
VS
S_I
2
C
VS
S
SD
R
A
M
_17
VD
D
SD
R
A
M
_
9
SD
R
A
M
_
8
VS
S
24
SD
A
25
SC
L
VD
D
VS
S
FS6050
48-pin SSOP
Figure 3: Pin Configuration (FS6051)
1 2 3 4 5 6 7 8
VD
D
SD
R
A
M
_
0
SD
R
A
M
_
1
VSS VD
D
SD
R
A
M
_
2
VS
S
S
DRA
M
_
1
4
S
DRA
M
_
1
5
VD
D
9
10 11 12 13 14
1516
SD
R
A
M
_
3
VSS
CL
K
_
I
N
VD
D
17181920212223
S
DRA
M_
1
6
VSS
V
DD_
I
2
C
VD
D
OES
DRA
M
_
1
3
S
DRA
M
_
1
2
VS
S
VD
D
28 27 26
V
SS_I
2
C
VS
S
S
DRA
M
_
1
7
24
SD
A
25
SC
L
FS6051
28-pin SOIC, SSOP
Additional pin configurations are noted on Page 2.