BCRTM-1
UT1553 BCRTM
FEATURES
p Comprehensive MIL-STD-1553 dual-redundant Bus
Controller (BC) and Remote Terminal (RT) and
Monitor (M) functions
p MIL-STD-1773 compatible
p Multiple message processing capability in BC
p Time tagging and message logging in RT and M modes
p Automatic polling and intermessage delay in
BC mode
p Programmable interrupt scheme and internally
generated interrupt history list
p Register-oriented architecture to enhance
programmability
p DMA memory interface with 64K addressability
p Internal self-test
p Radiation-hardened option available for 84-lead
flatpack package only
p Remote terminal operations in ASD/ENASD-certified
(SEAFAC)
p Available in 84-pin pingrid array, 84-lead flatpack, 84-
lead leadless chip-carrier
p Standard Microcircuit Drawing 5962-89577 available
- QML Q and V compliant
16
16
16
CONTROL
DMA/CPU
MESSAGE
RT/MONITOR
MESSAGE
BC PROTOCOL
HANDLER
INTERRUPT
CONVER-PARALLEL
SERIAL-TO-
CONVER-
TO-SERIALPARALLEL-
MODULE
DECODER
ENCODER/
CHANNEL
DUAL
BUS
TRANSFER
LOGIC
ADDRESS
16TIMEOUTTIMERON
CLOCK &
RESET
12MHz
MASTER
RESET
GENERATOR
ADDRESS
16
1553
HIGH-PRIORITY
RT ADDRESS
STANDARD INTERRUPT
HIGH-PRIORITY
INTERRUPT LOG
CURRENT COMMAND
BUILT-IN-TEST WORD
POLLING COMPARE
CURRENT BC (or M) BLOCK/
STATUS
CONTROL
REGISTERS
LIST POINTER
DATA
16
BUILT-
IN-
TEST
16
16
MONITOR ADDRESS
INTERRUPT STATUS
INTERRUPT ENABLE
SION
SION
PROTOCOL &
HANDLER
&
HANDLER
DATA
CHANNEL
B
1553
DATA
CHANNEL
A
LOGIC
HIGH-PRIORITY
STD PRIORITY LEVEL
STD PRIORITY PULSE
DMA ARBITRATION
REGISTER CONTROL
DUAL-PORT MEMORY CONTROL
RT DESCRIPTOR SPACE
ENABLE
BUILT-IN-TEST
START COMMAND
RESET COMMAND
CONTROL
MONITOR ADDRESS
SELECT (0-15)
MONITOR ADDRESS
Figure 1. BCRTM Block Diagram
SELECT (16-31)
RT TIMER
RESET COMMAND