November 1992
Revised January 1999
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© 1999 Fairchild Semiconductor Corporation DS011508.prf www.fairchildsemi.com
74ABT543
Octal Registered Transceiver with 3-STATE Outputs
General Description
The ABT543 octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either
direction. Separate Latch Enable and Output Enable inputs
are provided for each register to permit independent con-
trol of inputting and outputting in either direction of data
flow.
Features
a73 Back-to-back registers for storage
a73 Bidirectional data path
a73 A and B outputs have current sourcing capability of 32
mA and current sinking capability of 64 mA
a73 Separate controls for data flow in each direction
a73 Guaranteed output skew
a73 Guaranteed multiple output switching specifications
a73 Output switching specified for both 50 pF and 250 pF
loads
a73 Guaranteed simultaneous switching noise level and
dynamic threshold performance
a73 Guaranteed latchup protection
a73 High impedance glitch free bus loading during entire
power up and power down cycle
a73 Nondestructive hot insertion capability

Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignment for
SOIC, SSOP and TSSOP
Pin Descriptions
Order Number Package Number Package Description
74ABT543CSC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT543CMSA MSA24 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT543CMTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
OEAB, OEBA Output Enable Inputs
LEAB, LEBA Latch Enable Inputs
CEAB, CEBA Chip Enable Inputs
A
0
–A
7
Side A Inputs or 3-STATE Outputs
B
0
–B
7
Side B Inputs or 3-STATE Outputs