08140I-1
A0–A15
Address
Inputs
Y
Gating
524,288
Bit Cell
Matrix
X
Decoder
Y
Decoder
FINAL
Am27C512
512 Kilobit (64 K x 8-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
a73 Fast access time
— Speed options as fast as 55 ns
a73 Low power consumption
— 20 µA typical CMOS standby current
a73 JEDEC-approved pinout
a73 Single +5 V power supply
a73 ±10% power supply tolerance standard
a73 100% Flashrite™ programming
— Typical programming time of 8 seconds
a73 Latch-up protected to 100 mA from –1 V to
V
CC
+ 1 V
a73 High noise immunity
a73 Versatile features for simple interfacing
— Both CMOS and TTL input/output compatibility
— Two line control functions
a73 Standard 28-pin DIP, PDIP, and 32-pin PLCC
packages
GENERAL DESCRIPTION
The Am27C512 is a 512-Kbit, ultraviolet erasable pro-
grammable read-only memory. It is organized as 64K
words by 8 bits per word, operates from a single +5 V
supply, has a static standby mode, and features fast
single address location programming. Products are
available in windowed ceramic DIP packages, as well
as plastic one time programmable (OTP) PDIP and
PLCC packages.
Data can be typically accessed in less than 55 ns, al-
lowing high-performance microprocessors to operate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
thus eliminating bus contention in a multiple bus micro-
processor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 80 mW in active mode, and
100 µW in standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in
blocks, or at random. The device supports AMD’s
Flashrite programming algorithm (100 µs pulses), re-
sulting in a typical programming time of 8 seconds.
BLOCK DIAGRAM
CE#
OE#/V
PP
V
CC
V
SS
Data Outputs
DQ0–DQ7
Output
Buffers
Output Enable
Chip Enable
and
Prog Logic
Publication# 08140 Rev: I Amendment/0
Issue Date: May 1998