166 133 MHz
CLK
DQ
Power
down
OE
ZZ
Selection guide
Minimum cycle time
Maximum clock frequency
11/30/04, v.3.1 Alliance Semiconductor
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
Enable
delay
register
36/32
DQ[a:d]
–166 –133 Units
6 7.5 ns
• Organization: 262,144 words x 32 or 36 bits
• Fast clock speeds to 166 MHz
• Fast clock to data access: 3.5/4.0 ns
•Fast OE access time: 3.5/4.0 ns
• Fully synchronous register-to-register operation
• Single-cycle deselect
• Asynchronous output enable control
• Available in100-pin TQFP
• Individual byte write and global write
Logic block diagram
Q0
Q1
256K × 32/36
Memory
array
Burst logic
CLK
CLR
CE
Address
DQ
CE
CLK
DQ
d
CLK
DQ
Byte write
registers
register
DQ
c
CLK
DQ
Byte write
registers
DQ
b
CLK
DQ
Byte write
registers
DQ
a
CLK
DQ
Byte write
registers
Enable
CLK
DQ
registerCE
Output
registers
Input
registers
4
36/32
181618
18
GWE
BWE
BW
d
ADV
ADSC
ADSP
CLK
CE0
CE1
CE2
BW
c
BW
b
BW
a
A[17:0]
LBO
OE
CLK CLK
36/32
2 2
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
DDQ
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
• 30 mW typical standby power in power down mode
November 2004
®
AS7C33256PFS32A
AS7C33256PFS36A
3.3V 256K × 32/36 pipelined burst synchronous SRAM
Features
P. 1 of 20
Copyright ©Alliance Semiconductor. All rights reserved.
3.5 4 ns
475 425 mA
130 100 mA
30 30 mA