This Data Sheet states AMD’s current technical specificati
Sheet may be revised by subsequent versions or modifica
Refer to A
— Bank B contains ninety-six 32 Kword sectors outputs
n Low V
CC
write inhibit
n 48-Ball FBGA package
PRELIMINARY
Am29BDS643D
64 Megabit (4 M x 16-Bit)
CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
DISTINCTIVE CHARACTERISTICS
n Single 1.8 volt read, program and erase (1.7 to
1.9 volt)
n Multiplexed Data and Address for reduced I/O
count
— A0–A15 multiplexed as D0–D15
— Addresses are latched with AVD# control inputs
while CE# low
n Simultaneous Read/Write operation
— Data can be continuously read from one bank
while executing erase/program functions in other
bank
— Zero latency between read and write operations
n Read access times at 54 MHz/40 MHz
— Burst access times of 13.5/20 ns @ 30 pF
at industrial temperature range
— Asynchronous random access times
of 90/90 ns @ 30 pF
— Synchronous random access times
of 106/120 ns @ 30 pF
n Burst length
— Continuous linear burst
n Power dissipation (typical values, 8 bits
switching, C
L
= 30 pF)
— Burst Mode Read: 25 mA
— Simultaneous Operation: 40 mA
— Program/Erase: 15 mA
— Standby mode: 0.2 µA
n Sector Architecture
— Eight 4 Kword sectors and one hundred
twenty-seven 32 Kword sectors
— Bank A contains the eight 4 Kword sectors and
thirty-one 32 Kword sectors
n Sector Protection
— Software command sector locking
— WP# protects the last two boot sectors
— All sectors locked when V
PP
= V
IL
n Handshaking feature
— Provides host system with minimum possible
latency by monitoring RDY
n Software command set compatible with JEDEC
42.4 standards
— Backwards compatible with Am29F and Am29LV
families
n Minimum 1 million erase cycle guarantee
per sector
n 20-year data retention at 125°C
— Reliable operation for the life of the system
n Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
n Data# Polling and toggle bits
— Provides a software method of detecting
program and erase operation completion
n Erase Suspend/Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
n Hardware reset input (RESET#)
— Hardware method to reset the device for reading
array data
n CMOS compatible inputs, CMOS compatible
ons regarding the Product described herein. This Data
tions due to changes in technical specifications.
Publication# 23709 Rev: A Amendment/+3
Issue Date: December 21, 2000
MD’s Website (www.amd.com) for the latest information.