SN54AHCT373, SN74AHCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCLS239M – OCTOBER 1995 – REVISED JULY 2003
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
C0068 Inputs Are TTL-Voltage Compatible
C0068 Latch-Up Performance Exceeds 250 mA Per
JESD 17
C0068 ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SN54AHCT373 ...J OR W PACKAGE
SN74AHCT373 . . . DB, DGV, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
SN54AHCT373 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2D
2Q
3Q
3D
4D
1D 1Q OE
5Q 5D
8Q
4Q
GND
LE
V
CC
8D
7D
7Q
6Q
6D
description/ordering information
The ’AHCT373 devices are octal-transparent D-type latches. When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N Tube SN74AHCT373N SN74AHCT373N
SOIC DW
Tube SN74AHCT373DW
AHCT373 –
Tape and reel SN74AHCT373DWR
40°Cto85°C
SOP – NS Tape and reel SN74AHCT373NSR AHCT373
– C to 85
SSOP – DB Tape and reel SN74AHCT373DBR HB373
TSSOP PW
Tube SN74AHCT373PW
HB373 –
Tape and reel SN74AHCT373PWR
TVSOP – DGV Tape and reel SN74AHCT373DGVR HB373
CDIP – J Tube SNJ54AHCT373J SNJ54AHCT373J
–55°C to 125°C CFP – W Tube SNJ54AHCT373W SNJ54AHCT373W
LCCC – FK Tube SNJ54AHCT373FK SNJ54AHCT373FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright  2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.