a
Mixed Signal DSP Controller
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REV. 0
ADSP-21991
KEY FEATURES
ADSP-219x, 16-Bit, Fixed Point DSP Core with up to
160 MIPS Sustained Performance
40K Words of On-Chip RAM, Configured as 32K Words
On-Chip 24-Bit Program RAM and 8K Words On-Chip
16-Bit Data RAM
External Memory Interface
Dedicated Memory DMA Controller for Data/Instruction
Transfer between Internal/External Memory
Programmable PLL and Flexible Clock Generation
Circuitry Enables Full Speed Operation from Low
Speed Input Clocks
IEEE JTAG Standard 1149.1 Test Access Port Supports
On-Chip Emulation and System Debugging
8-Channel, 14-Bit Analog-to-Digital Converter System,
with up to 20 MSPS Sampling Rate (at 160 MHz Core
Clock Rate)
Three Phase 16-Bit Center Based PWM Generation Unit
with 12.5 ns Resolution at 160 MHz Core Clock (CCLK)
Rate
Dedicated 32-Bit Encoder Interface Unit with
Companion Encoder Event Timer
Dual 16-Bit Auxiliary PWM Outputs
16 General-Purpose Flag I/O Pins
Three Programmable 32-Bit Interval Timers
SPI Communications Port with Master or Slave
Operation
Synchronous Serial Communications Port (SPORT)
Capable of Software UART Emulation
Integrated Watchdog Timer
Dedicated Peripheral Interrupt Controller with Software
Priority Control
Multiple Boot Modes
Precision 1.0 V Voltage Reference
FUNCTIONAL BLOCK DIAGRAM
ADC
CONTROL
VREF
PIPELINE
FLASH ADC
CLOCK
GENERATOR/PLL
PM ADDRESS/DATA
DM ADDRESS/DATA
I/O
BUS
8K H1154716
DM RAM
32K H1154724
PM RAM
EXTERNAL
MEMORY
INTERFACE
(EMI)
TIMER 0
TIMER 1
TIMER 2
4K H1154724
PM ROM
ADSP-219x
DSP CORE
JTAG
TEST AND
EMULATION
ADDRESS
DATA
CONTROL
I/O REGISTERS
PWM
GENERATION
UNIT
ENCODER
INTERFACE
UNIT
(AND EET)
AUXILIARY
PWM
UNIT
FLAG
I/O
SPI SPORT
WATCHDOG
TIMER
INTERRUPT
CONTROLLER
(ICNTL)
POR
MEMORY DMA
CONTROLLER
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