1/7June 2003
a73 HIGH SPEED: t
PD
= 3.6ns (TYP.) at V
CC
=5V
a73 LOW POWER DISSIPATION:
I
CC
=1µA(MAX.) at T
A
=25°C
a73 COMPATIBLE WITH TTL OUTPUTS:
V
IH
=2V(MIN),V
IL
=0.8V(MAX)
a73 POWER DOWN PROTECTION ON INPUT
a73 SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
|=I
OL
=8mA(MIN)atV
CC
=4.5V
a73 BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
a73 OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
a73 IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74V2T70 is an advanced high-speed CMOS
TRIPLE BUFFER fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology.
The internal circuit is composed of 2 stages
including buffer output, which provide high noise
immunity and stable output.
Power down protection is provided on input and 0
to 7V can be accepted on input with no regard to
the supply voltage. This device can be used to
interface5Vto3V.
74V2T70
TRIPLE BUFFER
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE T & R
SOT23-8L 74V2T70STR
SOT23-8L