1/11July 2004
a73 HIGH SPEED:
t
PD
= 5.6 ns (TYP.) at V
CC
= 3.3 V
a73 COMPATIBLE WITH TTL OUTPUTS
a73 LOW POWER DISSIPATION:
I
CC
= 2µA(MAX.) at T
A
=25°C
a73 LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
a73 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
a73 SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12 mA (MIN) at V
CC
= 3.0 V
a73 PCI BUS LEVELS GUARANTEED AT 24 mA
a73 BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL

a73 OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
a73 PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 08
a73 IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ08 is a low voltage CMOS QUAD
2-INPUT AND GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low noise
3.3V applications.
The internal circuit is composed of 2 stages
including buffer output, which enables high noise
immunity and stable output.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVQ08
LOW VOLTAGE CMOS QUAD 2-INPUT AND GATE

Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE T & R
SOP 74LVQ08MTR
TSSOP 74LVQ08TTR
TSSOPSOP
Rev. 5