1/10July 2001
a73 HIGH SPEED: t
PD
= 4.7ns (TYP.) at V
CC
= 5V
a73 LOW POWER DISSIPATION:
I
CC
= 1µA(MAX.) at T
A
=25°C
a73 COMPATIBLE WITH TTL OUTPUTS:
V
IH
= 2V (MIN), V
IL
= 0.8V (MAX)
a73 POWER DOWN PROTECTION ON INPUTS
a73 SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8mA (MIN) at V
CC
= 4.5V
a73 BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL

a73 OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
a73 IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74V1T77 is an advanced high-speed CMOS
SINGLE D-TYPE LATCH fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology. It is designed to
operate from 4.5V to 5.5V, making this device
ideal for portable applications.
The single D-Type latch is controlled by an Latch
Enable Input (LE). While the LE input is held at a
high level, the Q output will follow the data input
precisely. When the LE input is taken low the Q
output is latched precisely at the logic level of D
data input.
Power down protection is provided on inputs and
0 to 7V can be accepted on inputs with no regard
to the supply voltage. This device can be used to
interface 5V to 3V.
It’s available in the commercial and extended
temperature range.
All inputs and output are equipped with protection
circuits against static discharge, giving them ESD
immunity and transient excess voltage.
74V1T77
SINGLE D-TYPE LATCH

PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE T & R
SOT23-5L 74V1T77STR
SOT323-5L 74V1T77CTR
SOT323-5LSOT23-5L