74LCX273
器件描述：Low-Voltage Octal D Flip-Flop with 5V Tolerant Inputs and Outputs
器件厂商：NSC [National Semiconductor]
文件大小：63.33KB，共2页
Sponsor by e络盟器件资料摘要：
TL/F/12640
74LCX273
Low-Voltage
Octal
D
Flip-Flop
with
5V
Tolerant
Inputs
and
Outputs
ADVANCE INFORMATION
November 1996
74LCX273
Low-Voltage Octal D Flip-Flop
with 5V Tolerant Inputs and Outputs
General Description
The LCX273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) input load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock tran-
sition, is transferred to the corresponding flip-flop’s Q out-
put.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
The device is designed for low voltage (3.3V) V
CC
applica-
tions with capability of interfacing to a 5V signal environ-
ment. The LCX273 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Features
Y
5V tolerant inputs and outputs
Y
10 mAI
CCQ
max
Y
Power-down high impedance inputs and outputs
Y
Supports live insertion/withdrawal
Y
2.0V–3.6V V
CC
supply operation
Y
g24 mA output drive
Y
Implements patented Quiet Series
TM
noise/EMI
reduction circuitry
Y
Functionally compatible with the 74 series 273
Y
Latch-up performance exceeds 500 mA
Y
ESD performance:
Human Body Model
l
2000V
Machine Model
l
200V
Logic Symbols
TL/F/12640–1
IEEE/IEC
TL/F/12640–2
Connection Diagram
Pin Assignment for
SOIC, SSOP and TSSOP
TL/F/12640–3
Pin Names Description
D
0
–D
7
Data Inputs
MR Master Reset
CP Clock Pulse Input
Q
0
–Q
7
Data Outputs
SOIC JEDEC SOIC EIAJ SSOP Type II TSSOP JEDEC
Order Number 74LCX273WM 74LCX273SJ 74LCX273MSA 74LCX273MTC
74LCX273WMX 74LCX273SJX 74LCX273MSAX 74LCX273MTCX
See NS Package Number M20B M20D MSA20 MTC20
TRI-STATE is a registered trademark of National Semiconductor Corporation.
Quiet SeriesTM is a trademark of National Semiconductor Corporation.
C
1996 National Semiconductor Corporation RRD-B30M17/Printed in U. S. A. http://www.national.com
74LCX273
Low-Voltage
Octal
D
Flip-Flop
with
5V
Tolerant
Inputs
and
Outputs
ADVANCE INFORMATION
November 1996
74LCX273
Low-Voltage Octal D Flip-Flop
with 5V Tolerant Inputs and Outputs
General Description
The LCX273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) input load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock tran-
sition, is transferred to the corresponding flip-flop’s Q out-
put.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
The device is designed for low voltage (3.3V) V
CC
applica-
tions with capability of interfacing to a 5V signal environ-
ment. The LCX273 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Features
Y
5V tolerant inputs and outputs
Y
10 mAI
CCQ
max
Y
Power-down high impedance inputs and outputs
Y
Supports live insertion/withdrawal
Y
2.0V–3.6V V
CC
supply operation
Y
g24 mA output drive
Y
Implements patented Quiet Series
TM
noise/EMI
reduction circuitry
Y
Functionally compatible with the 74 series 273
Y
Latch-up performance exceeds 500 mA
Y
ESD performance:
Human Body Model
l
2000V
Machine Model
l
200V
Logic Symbols
TL/F/12640–1
IEEE/IEC
TL/F/12640–2
Connection Diagram
Pin Assignment for
SOIC, SSOP and TSSOP
TL/F/12640–3
Pin Names Description
D
0
–D
7
Data Inputs
MR Master Reset
CP Clock Pulse Input
Q
0
–Q
7
Data Outputs
SOIC JEDEC SOIC EIAJ SSOP Type II TSSOP JEDEC
Order Number 74LCX273WM 74LCX273SJ 74LCX273MSA 74LCX273MTC
74LCX273WMX 74LCX273SJX 74LCX273MSAX 74LCX273MTCX
See NS Package Number M20B M20D MSA20 MTC20
TRI-STATE is a registered trademark of National Semiconductor Corporation.
Quiet SeriesTM is a trademark of National Semiconductor Corporation.
C
1996 National Semiconductor Corporation RRD-B30M17/Printed in U. S. A. http://www.national.com