Ultra Low Power/High Speed CMOS SRAM
1M X 16 bit BH616UV1610BSI
R0201-BH616UV1610 Revision 1.0
Jul. 20051
n FEATURES
Wide VCC low operation voltage : 1.65V ~ 3.6V
Ultra low power consumption :
VCC = 3.0V Operation current : 5.0mA at 70ns at 25OC
1.5mA at 1MHz at 25OC
Standby current : 3uA at 25OC
VCC = 2.0V Data retention current : 3uA at 25OC
High speed access time :
-70 70ns at 1.8V at 85OC
Automatic power down when chip is deselected
Easy expansion with CE1, CE2 and OE options
I/O Configuration x8/x16 selectable by LB and UB pin.
Three state outputs and TTL compatible
Fully static operation, no clock, no refreash
Data retention supply voltage as low as 1.0V
n DESCRIPTION
The BH616UV1610 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 1,048,576 by 16 bits and
operates in a wide range of 1.65V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with typical operating current of 1.5mA at
1MHz at 3.0V/25OC and maximum access time of 70ns at 1.8V/85OC.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2) and active LOW output
enable (OE) and three-state output drivers.
The BH616UV1610 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BH616UV1610 is made with two chips of 8Mbit SRAM by stacked
multi-chip-package.
The BH616UV1610 is available in 48-ball BGA package.

n PRODUCT FAMILY
POWER CONSUMPTION SPEED
(ns) STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
PRODUCT
FAMILY
OPERATING
TEMPERATURE
VCC
RANGE
VCC=1.8~3.6V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V
PKG TYPE
+0OC to +70OC 70 20uA 15uA 10mA 7mA
BH616UV1610AI
-25OC to +85OC
1.65V ~ 3.6V
70 25uA 20uA 10mA 7mA
BGA-48-0608


n PIN CONFIGURATIONS




















n BLOCK DIAGRAM







Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Detailed product characteristic test report is available upon request and being accepted.
G
H
F
E
D
C
B
A
1 2 3 4 5 6
A9 A11 A10 NC
A12
A14
A13
A15
WE
DQ13 DQ5
DQ7
DQ6
A17
A16
A7
VSS
VCC
DQ12
DQ11
DQ4
DQ3
VSS
A5
OE
A3
A0
A6
A4
A1 A2 CE2
UB
DQ10 DQ1
CE1
DQ2
DQ0
48-ball BGA top view
LB
DQ8
DQ9
VSS
VCC
DQ14
DQ15
A18
A19
A8
Address
Input
Buffer
Row
Decoder
Memory Array

1024 x 16384
Column I/O
Write Driver
Sense Amp
Column Decoder
Address Input Buffer
A15 A16 A2 A1
Data
Input
Buffer
Control
DQ0
.
.
.
.
.
.
DQ15
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
16
16
16
16
10
1024
16384
1024 10
A19
Data
Output
Buffer
A13
CE2, CE1
WE
OE
UB
LB
VCC
VSS
A0
.
.
.
.
.
.
A14 A17 A18