© 2004 Fairchild Semiconductor Corporation DS500126 www.fairchildsemi.com
March 1998
Revised October 2004
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74VCX16601
Low Voltage 18-Bit Universal Bus Transceivers
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX16601 is an 18-bit universal bus transceiver which
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. The clock can be con-
trolled by the clock-enable (CLKENAB and CLKENBA)
inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is
LOW, the A data is latched if CLKAB is held at a HIGH-to-
LOW logic level. If LEAB is LOW, the A bus data is stored
in the latch/flip-flop on the LOW-to-HIGH transition of
CLKAB. When OEAB is LOW, the outputs are active. When
OEAB is HIGH, the outputs are in the high-impedance
state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, CLKBA and CLKENBA.
The VCX16601 is designed for low voltage (1.4V to 3.6V)
V
CC
applications with I/O capability up to 3.6V.
The VCX16601 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
a73 1.4V to 3.6V V
CC
supply operation
a73 3.6V tolerant inputs and outputs
a73 t
PD
(A to B, B to A)
2.9 ns max for 3.0V to 3.6V V
CC
a73 Power-down high impedance inputs and outputs
a73 Supports live insertion/withdrawal (Note 1)
a73 Static Drive (I
OH
/I
OL
)
±24 mA @ 3.0V V
CC
a73 Uses patented noise/EMI reduction circuitry
a73 Latchup performance exceeds 300 mA
a73 ESD performance:
Human body model > 2000V
Machine model >200V
a73 Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.

Ordering Code:
Note 2: BGA package available in Tape and Reel only.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number Package Number Package Description
74VCX16601GX
(Note 2)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
74VCX16601MTD
(Note 3)
MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide