1. General description
The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin
compatible with the HEF4040B series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP),
an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to
Q11). The counter advances on the HIGH-to-LOW transition of CP.
A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the
state of CP.
Each counter stage is a static toggle flip-flop.
2. Features
a73 Multiple package options
a73 Complies with JEDEC standard no. 7A
a73 ESD protection:
a78 HBM JESD22-A114-C exceeds 2000 V
a78 MM JESD22-A115-A exceeds 200 V
a73 Specified from −40 °Cto+85°C and from −40 °C to +125 °C
3. Applications
a73 Frequency dividing circuits
a73 Time delay circuits
a73 Control counters
4. Quick reference data
74HC4040; 74HCT4040
12-stage binary ripple counter
Rev. 03 — 14 September 2005 Product data sheet
Table 1: Quick reference data
GND = 0 V; T
amb
=25°C; t
r
=t
f
= 6 ns.
Symbol Parameter Conditions Min Typ Max Unit
Type 74HC4040
t
PHL
, t
PLH
propagation delay
CP to Q0 C
L
= 15 pF; V
CC
= 5 V - 14 - ns
Qn to Qn+1 C
L
= 15 pF; V
CC
=5V - 8 - ns