Features
a174 Data retention in the absence of
power
a174 Automatic write-protection
during power-up/power-down
cycles
a174 Industry-standard 28-pin 8K x 8
pinout
a174 Conventional SRAM operation;
unlimited write cycles
a174 10-year minimum data retention
in absence of power
a174 Battery internally isolated until
power is applied
Pin Connections
General Description
The CMOS bq4010 is a nonvolatile
65,536-bit static RAM organized as
8,192 words by 8 bits. The integral
control circuitry and lithium energy
source provide reliable nonvolatility
coupled with the unlimited write
cycles of standard SRAM.
The control circuitry constantly
monitors the single 5V supply for an
out-of-tolerance condition. When VCC
falls out of tolerance, the SRAM is
unconditionally write-protected to
prevent inadvertent write operation.
At this time the integral energy
source is switched on to sustain the
memory until after VCC returns valid.
The bq4010 uses an extremely low
standby current CMOS SRAM,
coupled with a small lithium coin
cell to provide nonvolatility without
long write-cycle times and the write-
cycle limitations associated with
EEPROM.
The bq4010 requires no external cir-
cuitry and is socket-compatible with
industry-standard SRAMs and most
EPROMs and EEPROMs.
Pin Names
A0 –A12 Address inputs
DQ0–DQ7 Data input/output
CE Chip enable input
OE Output enable input
WE Write enable input
NC No connect
VCC +5 volt supply input
VSS Ground
8Kx8 Nonvolatile SRAM
bq4010/bq4010Y
Sept. 1996 D
Block Diagram
Selection Guide
Part
Number
Maximum
Access
Time (ns)
Negative
Supply
Tolerance
Part
Number
Maximum
Access
Time (ns)
Negative
Supply
Tolerance
bq4010Y -70 70 -10%
bq4010 -85 85 -5% bq4010Y -85 85 -10%
bq4010 -150 150 -5% bq4010Y -150 150 -10%
bq4010 -200 200 -5% bq4010Y -200 200 -10%
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