1/12September 2004
a73 5V TOLERANT INPUTS AND OUTPUTS
a73 HIGH SPEED:
t
PD
= 5.2 ns (MAX.) at V
CC
= 3V
a73 POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
a73 SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3V
a73 PCI BUS LEVELS GUARANTEED AT 24 mA
a73 BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL

a73 OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
a73 PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 125
a73 LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
a73 ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LCX125 is a low voltage CMOS QUAD
BUS BUFFER fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for both inputs and outputs.
The device requires the 3-STATE control input G
to be set high to place the output in to the high
impedance state.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LCX125
LOW VOLTAGE CMOS QUAD BUS BUFFER (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS

Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE T & R
SOP 74LCX125MTR
TSSOP 74LCX125TTR
TSSOPSOP
Rev. 5