74LS221N
器件资料摘要：
Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1 Publication Order Number:
SN74LS221/D
C0083C0078C0055C0052C0076C0083C0050C0050C0049
C0068C0117C0097C0108 C0077C0111C0110C0111C0115C0116C0097C0098C0108C0101
C0077C0117C0108C0116C0105C0118C0105C0098C0114C0097C0116C0111C0114C0115 C0119C0105C0116C0104
C0083C0099C0104C0109C0105C0116C0116C0045C0084C0114C0105C0103C0103C0101C0114 C0073C0110C0112C0117C0116C0115
Each multivibrator of the LS221 features a negative-transition-
triggered input and a positive-transition-triggered input either of
which can be used as an inhibit input.
Pulse triggering occurs at a voltage level and is not related to the
transition time of the input pulse. Schmitt-trigger input circuitry for B
input allows jitter-free triggering for inputs as slow as 1 volt/second,
providing the circuit with excellent noise immunity. A high immunity
to V
CC
noise is also provided by internal latching circuitry.
Once triggered, the outputs are independent of further transitions of
the inputs and are a function of the timing components. The output
pulses can be terminated by the overriding clear. Input pulse width
may be of any duration relative to the output pulse width. Output pulse
width may be varied from 35 nanoseconds to a maximum of 70 s by
choosing appropriate timing components. With R
ext
= 2.0 kΩ and C
ext
= 0, a typical output pulse of 30 nanoseconds is achieved. Output rise
and fall times are independent of pulse length.
Pulse width stability is achieved through internal compensation and
is virtually independent of V
CC
and temperature. In most applications,
pulse stability will only be limited by the accuracy of external timing
components.
Jitter-free operation is maintained over the full temperature and V
CC
ranges for greater than six decades of timing capacitance (10 pF to 10
µF), and greater than one decade of timing resistance (2.0 to 100 kΩ
for the SN74LS221). Pulse width is defined by the relationship:
t
w
(out) = C
ext
R
ext
ln 2.0 ≈ 0.7 C
ext
R
ext
; where t
W
is in ns if C
ext
is in
pF and R
ext
is in kΩ. If pulse cutoff is not critical, capacitance up to
1000 µF and resistance as low as 1.4 kΩ may be used. The range of
jitter-free pulse widths is extended if V
CC
is 5.0 V and 25°C
temperature.
• SN74LS221 is a Dual Highly Stable One-Shot
• Overriding Clear Terminates Output Pulse
• Pin Out is Identical to SN74LS123
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage 4.75 5.0 5.25 V
T
A
Operating Ambient
Temperature Range
0 25 70 °C
I
OH
Output Current – High –0.4 mA
I
OL
Output Current – Low 8.0 mA
LOW
POWER
SCHOTTKY
Device Package Shipping
ORDERING INFORMATION
SN74LS221N 16 Pin DIP 2000 Units/Box
SN74LS221D 16 Pin
SOIC
D SUFFIX
CASE 751B
http://onsemi.com
2500/Tape & Reel
PLASTIC
N SUFFIX
CASE 648
16
1
16
1
December, 1999 – Rev. 6
1 Publication Order Number:
SN74LS221/D
C0083C0078C0055C0052C0076C0083C0050C0050C0049
C0068C0117C0097C0108 C0077C0111C0110C0111C0115C0116C0097C0098C0108C0101
C0077C0117C0108C0116C0105C0118C0105C0098C0114C0097C0116C0111C0114C0115 C0119C0105C0116C0104
C0083C0099C0104C0109C0105C0116C0116C0045C0084C0114C0105C0103C0103C0101C0114 C0073C0110C0112C0117C0116C0115
Each multivibrator of the LS221 features a negative-transition-
triggered input and a positive-transition-triggered input either of
which can be used as an inhibit input.
Pulse triggering occurs at a voltage level and is not related to the
transition time of the input pulse. Schmitt-trigger input circuitry for B
input allows jitter-free triggering for inputs as slow as 1 volt/second,
providing the circuit with excellent noise immunity. A high immunity
to V
CC
noise is also provided by internal latching circuitry.
Once triggered, the outputs are independent of further transitions of
the inputs and are a function of the timing components. The output
pulses can be terminated by the overriding clear. Input pulse width
may be of any duration relative to the output pulse width. Output pulse
width may be varied from 35 nanoseconds to a maximum of 70 s by
choosing appropriate timing components. With R
ext
= 2.0 kΩ and C
ext
= 0, a typical output pulse of 30 nanoseconds is achieved. Output rise
and fall times are independent of pulse length.
Pulse width stability is achieved through internal compensation and
is virtually independent of V
CC
and temperature. In most applications,
pulse stability will only be limited by the accuracy of external timing
components.
Jitter-free operation is maintained over the full temperature and V
CC
ranges for greater than six decades of timing capacitance (10 pF to 10
µF), and greater than one decade of timing resistance (2.0 to 100 kΩ
for the SN74LS221). Pulse width is defined by the relationship:
t
w
(out) = C
ext
R
ext
ln 2.0 ≈ 0.7 C
ext
R
ext
; where t
W
is in ns if C
ext
is in
pF and R
ext
is in kΩ. If pulse cutoff is not critical, capacitance up to
1000 µF and resistance as low as 1.4 kΩ may be used. The range of
jitter-free pulse widths is extended if V
CC
is 5.0 V and 25°C
temperature.
• SN74LS221 is a Dual Highly Stable One-Shot
• Overriding Clear Terminates Output Pulse
• Pin Out is Identical to SN74LS123
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage 4.75 5.0 5.25 V
T
A
Operating Ambient
Temperature Range
0 25 70 °C
I
OH
Output Current – High –0.4 mA
I
OL
Output Current – Low 8.0 mA
LOW
POWER
SCHOTTKY
Device Package Shipping
ORDERING INFORMATION
SN74LS221N 16 Pin DIP 2000 Units/Box
SN74LS221D 16 Pin
SOIC
D SUFFIX
CASE 751B
http://onsemi.com
2500/Tape & Reel
PLASTIC
N SUFFIX
CASE 648
16
1
16
1