C0083C0078C0055C0052C0076C0086C0067C0049C0071C0049C0050C0053C0262C0081C0049
C0083C0073C0078C0071C0076C0069 C0066C0085C0083 C0066C0085C0070C0070C0069C0082 C0071C0065C0084C0069
C0087C0073C0084C0072 C0051C0262C0083C0084C0065C0084C0069 C0079C0085C0084C0080C0085C0084
SGES002A − APRIL 2003 − REVISED MAY 2004
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
C0068 Qualification in Accordance With
AEC-Q100
†
C0068 Qualified for Automotive Applications
C0068 Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
C0068 Available in the Texas Instruments
NanoStar and NanoFree Packages
C0068 Supports 5-V V
CC
Operation
C0068 Inputs Accept Voltages to 5.5 V
C0068 Max t
pd
of 3.7 ns at 3.3 V
C0068 Low Power Consumption, 10-µA Max I
CC
C0068 ±24-mA Output Drive at 3.3 V
†
Contact factory for details. Q100 qualification data available on
request.
C0068 I
off
Supports Partial-Power-Down Mode
Operation
C0068 Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
C0068 ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This bus buffer gate is designed for 1.65-V to 5.5-V V
CC
operation.
The SN74LVC1G125 is a single line driver with a 3-state output. The output is disabled when the output-enable
(OE) input is high.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
T
A
PACKAGE
‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
§
−40°C to 125°C SOT (SC-70) − DCK Reel of 2875 1P1G125QDCKRQ1 CM_
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
§
DCK: The actual top-side marking has one additional character that designates the assembly/test site.
FUNCTION TABLE
INPUTS
OUTPUT
OE A
Y
L H H
L LL
H X Z
Copyright  2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
DCK PACKAGE
(TOP VIEW)
1
2
3
5
4
OE
A
GND
V
CC
Y
C0080C0082C0079C0068C0085C0067C0084C0073C0079C0078 C0068C0065C0084C0065 C0105C0110C0102C0111C0114C0109C0097C0116C0105C0111C0110 C0105C0115 C0099C0117C0114C0114C0101C0110C0116 C0097C0115 C0111C0102 C0112C0117C0098C0108C0105C0099C0097C0116C0105C0111C0110 C0100C0097C0116C0101C0046
C0080C0114C0111C0100C0117C0099C0116C0115 C0099C0111C0110C0102C0111C0114C0109 C0116C0111 C0115C0112C0101C0099C0105C0102C0105C0099C0097C0116C0105C0111C0110C0115 C0112C0101C0114 C0116C0104C0101 C0116C0101C0114C0109C0115 C0111C0102 C0084C0101C0120C0097C0115 C0073C0110C0115C0116C0114C0117C0109C0101C0110C0116C0115
C0115C0116C0097C0110C0100C0097C0114C0100 C0119C0097C0114C0114C0097C0110C0116C0121C0046 C0080C0114C0111C0100C0117C0099C0116C0105C0111C0110 C0112C0114C0111C0099C0101C0115C0115C0105C0110C0103 C0100C0111C0101C0115 C0110C0111C0116 C0110C0101C0099C0101C0115C0115C0097C0114C0105C0108C0121 C0105C0110C0099C0108C0117C0100C0101
C0116C0101C0115C0116C0105C0110C0103 C0111C0102 C0097C0108C0108 C0112C0097C0114C0097C0109C0101C0116C0101C0114C0115C0046