74LCX74BQX
器件描述：Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：89.07KB，共11页
Sponsor by e络盟器件资料摘要：
© 2005 Fairchild Semiconductor Corporation DS012414 www.fairchildsemi.com
March 1995
Revised February 2005
7
4LCX74 Low
V
o
l
t
age
Dual
D-T
ype
Posi
ti
ve Edg
e
-T
r
i
gger
ed F
l
i
p
-Fl
op wi
th
5V T
o
l
e
ran
t
Input
s
74LCX74
Low Voltage Dual D-Type Positive
Edge-Triggered Flip-Flop with 5V Tolerant Inputs
General Description
The LCX74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on the
positive edge of the clock pulse. After the Clock Pulse input
threshold voltage has been passed, the Data input is
locked out and information present will not be transferred to
the outputs until the next rising edge of the Clock Pulse
input.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and
Q HIGH
Features
a73 5V tolerant inputs
a73 2.3V–3.6V V
CC
specifications provided
a73 7.0 ns t
PD
max (V
CC
c32 3.3V), 10 c80A I
CC
max
a73 Power down high impedance inputs and outputs
a73 c11424 mA output drive (V
CC
c32 3.0V)
a73 Implements patented noise/EMI reduction circuitry
a73 Latch-up performance exceeds JEDEC 78 conditions
a73 ESD performance:
Human body model c33 2000V
Machine model c33 200V
a73 Leadless Pb-Free DQFN package
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: DQFN package available in Tape and Reel only.
Note 2: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Order Number
Package
Package Description
Number
74LCX74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX74MX_NL
(Note 2)
M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX74SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX74BQX
(Note 1)
MLP014A Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
74LCX74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LCX74MTCX_NL
(Note 2)
MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
March 1995
Revised February 2005
7
4LCX74 Low
V
o
l
t
age
Dual
D-T
ype
Posi
ti
ve Edg
e
-T
r
i
gger
ed F
l
i
p
-Fl
op wi
th
5V T
o
l
e
ran
t
Input
s
74LCX74
Low Voltage Dual D-Type Positive
Edge-Triggered Flip-Flop with 5V Tolerant Inputs
General Description
The LCX74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on the
positive edge of the clock pulse. After the Clock Pulse input
threshold voltage has been passed, the Data input is
locked out and information present will not be transferred to
the outputs until the next rising edge of the Clock Pulse
input.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and
Q HIGH
Features
a73 5V tolerant inputs
a73 2.3V–3.6V V
CC
specifications provided
a73 7.0 ns t
PD
max (V
CC
c32 3.3V), 10 c80A I
CC
max
a73 Power down high impedance inputs and outputs
a73 c11424 mA output drive (V
CC
c32 3.0V)
a73 Implements patented noise/EMI reduction circuitry
a73 Latch-up performance exceeds JEDEC 78 conditions
a73 ESD performance:
Human body model c33 2000V
Machine model c33 200V
a73 Leadless Pb-Free DQFN package
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: DQFN package available in Tape and Reel only.
Note 2: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Order Number
Package
Package Description
Number
74LCX74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX74MX_NL
(Note 2)
M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX74SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX74BQX
(Note 1)
MLP014A Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
74LCX74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LCX74MTCX_NL
(Note 2)
MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide