© 2000 Fairchild Semiconductor Corporation DS006525 www.fairchildsemi.com
September 1986
Revised February 2000
DM7473 Dual

Mast
er-
S
l
ave J-K Fl
ip-
F
lops wit
h

Cl
ear and Com
p
l
e
mentar
y
Out
puts
DM7473
Dual Master-Slave J-K Flip-Flops
with Clear and Complementary Outputs
General Description
This device contains two independent positive pulse trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops after a complete clock
pulse. While the clock is LOW the slave is isolated from the
master. On the positive transition of the clock, the data
from the J and K inputs is transferred to the master. While
the clock is HIGH the J and K inputs are disabled. On the
negative transition of the clock, the data from the master is
transferred to the slave. The logic states of the J and K
inputs must not be allowed to change while the clock is
HIGH. Data transfers to the outputs on the falling edge of
the clock pulse. A LOW logic level on the clear input will
reset the outputs regardless of the logic states of the other
inputs.

Ordering Code:
Connection Diagram Function Table
H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level
c12 = Positive pulse data. the J and K inputs must be held constant while
the clock is HIGH. Data is transferred to the outputs on the falling
edge of the clock pulse.
Q
0
= The output logic level before the indicated input conditions were
established.
Toggle = Each output changes to the complement of its previous level on
each HIGH level clock pulse.
Order Number Package Number Package Description
DM7473N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Outputs
CLR CLK J K Q Q
LXXXL H
H c12 LL Q
0
Q
0
H c12 HL H L
H c12 LH L H
H c12 H H Toggle