1/12July 2004
a73 HIGH SPEED:
t
PD
=5.8 ns (TYP.) at V
CC
= 3.3 V
a73 COMPATIBLE WITH TTL OUTPUTS
a73 LOW POWER DISSIPATION:
I
CC
= 4 µA (MAX.) at T
A
=25°C
a73 LOW NOISE:
V
OLP
= 0.4V (TYP.) at V
CC
= 3.3V
a73 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
a73 SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 3.0 V
a73 PCI BUS LEVELS GUARANTEED AT 24 mA
a73 BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL

a73 OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
a73 PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 541
a73 IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ541 is a low voltage CMOS OCTAL
BUS BUFFER with 3 STATE OUTPUTS NON
INVERTED fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low noise
3.3V applications.
The 3-STATE control gate operates as two input
and such that if either G1 and G2 are high, all
eight outputs are in the high impedance state. In
order to enhance PC board layout, the 74AC541
offers a pinout having inputs and outputs on
opposite side of the package.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVQ541
OCTAL BUS BUFFER
WITH 3 STATE OUTPUTS (NON INVERTED)

Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE T & R
SOP 74LVQ541MTR
TSSOP 74LVQ541TTR
TSSOPSOP
Rev. 2