ADSP-21262
器件资料摘要：
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
SHARC
®
Processor
ADSP-21262
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high precision signal processing
applications
The ADSP-21262 SHARC DSP is code compatible with all
other SHARC DSPs
Single-Instruction Multiple-Data (SIMD) computational archi-
tecture—two 32-bit IEEE floating-point/32-bit fixed-
point/40-bit extended precision floating-point computa-
tional units, each with a multiplier, ALU, shifter, and
register file
High bandwidth I/O—A parallel port, SPI port, six serial
ports, digital audio interface (DAI), and JTAG
DAI incorporates two precision clock generators (PCGs), an
input data port (IDP) which includes the parallel data
acquisition port (PDAP), and three programmable timers,
all under software control through the signal routing unit
(SRU)
On-chip memory—2M bits of on-chip SRAM and a dedicated
4M bits of on-chip mask-programmable ROM
Six independent synchronous serial ports provide a variety
of serial communication protocols including TDM and I
2
S
modes
The ADSP-21262 is available with a 200 MHz core instruction
rate. For complete ordering information, see Ordering
Guide on Page 44.
Figure 1. Functional Block Diagram
ADDR DATA
PX REGISTER
6
JTAG TEST & EMULATION
20
3
SERIAL PORTS (6)
INPUT
DATA PORTS (8)
PARALLEL DATA
ACQUISITION PORT
TIMERS (3)
SIGNAL
RO UTI NG
UNIT
PRECISI ON CLO CK
GENERATORS (2)
DIGITAL AUDIO INTERFACE
3
16
ADDRESS/
DATA BUS/ GPIO
CONTROL/GPIO
PARALLEL
PORT
IOP
REGISTERS
(MEMORY MAPPED)
CO NTROL,
STATUS,
DATA BUFFERS
4
SPI PO RT (1)
DMA CONTROLLER
22 CHANNELS
4
GPIO FLAGS/
IRQ/TIMEXP
I/O PROCESSOR
PROCESSING
ELEMENT
(PEY)
PROCESSING
EL EMENT
(PEX)
TIMER
INSTRUCTION
CACHE
32 H11547 48-BIT
DAG1
8 H11547 4 H11547 32
DA G2
8 H11547 4 H11547 32
32
P M ADDRES S BUS
DM ADDRESS BUS
PM DATA BUS
DMDATA BUS
64
64
CORE PROCESSOR
PROGRAM
SEQUENCER
ADDR DATA
SRAM
1MBIT ROM
2MBIT
DUAL PORTED MEMORY
BLOCK 0
SRAM
1MBIT ROM
2MBIT
DUAL PORTED MEMORY
BLO CK 1
S
IOD
(32)
IOA
(18)
32
SHARC
®
Processor
ADSP-21262
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high precision signal processing
applications
The ADSP-21262 SHARC DSP is code compatible with all
other SHARC DSPs
Single-Instruction Multiple-Data (SIMD) computational archi-
tecture—two 32-bit IEEE floating-point/32-bit fixed-
point/40-bit extended precision floating-point computa-
tional units, each with a multiplier, ALU, shifter, and
register file
High bandwidth I/O—A parallel port, SPI port, six serial
ports, digital audio interface (DAI), and JTAG
DAI incorporates two precision clock generators (PCGs), an
input data port (IDP) which includes the parallel data
acquisition port (PDAP), and three programmable timers,
all under software control through the signal routing unit
(SRU)
On-chip memory—2M bits of on-chip SRAM and a dedicated
4M bits of on-chip mask-programmable ROM
Six independent synchronous serial ports provide a variety
of serial communication protocols including TDM and I
2
S
modes
The ADSP-21262 is available with a 200 MHz core instruction
rate. For complete ordering information, see Ordering
Guide on Page 44.
Figure 1. Functional Block Diagram
ADDR DATA
PX REGISTER
6
JTAG TEST & EMULATION
20
3
SERIAL PORTS (6)
INPUT
DATA PORTS (8)
PARALLEL DATA
ACQUISITION PORT
TIMERS (3)
SIGNAL
RO UTI NG
UNIT
PRECISI ON CLO CK
GENERATORS (2)
DIGITAL AUDIO INTERFACE
3
16
ADDRESS/
DATA BUS/ GPIO
CONTROL/GPIO
PARALLEL
PORT
IOP
REGISTERS
(MEMORY MAPPED)
CO NTROL,
STATUS,
DATA BUFFERS
4
SPI PO RT (1)
DMA CONTROLLER
22 CHANNELS
4
GPIO FLAGS/
IRQ/TIMEXP
I/O PROCESSOR
PROCESSING
ELEMENT
(PEY)
PROCESSING
EL EMENT
(PEX)
TIMER
INSTRUCTION
CACHE
32 H11547 48-BIT
DAG1
8 H11547 4 H11547 32
DA G2
8 H11547 4 H11547 32
32
P M ADDRES S BUS
DM ADDRESS BUS
PM DATA BUS
DMDATA BUS
64
64
CORE PROCESSOR
PROGRAM
SEQUENCER
ADDR DATA
SRAM
1MBIT ROM
2MBIT
DUAL PORTED MEMORY
BLOCK 0
SRAM
1MBIT ROM
2MBIT
DUAL PORTED MEMORY
BLO CK 1
S
IOD
(32)
IOA
(18)
32