SN74LVC1G125
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS

SCES223C – APRIL 1999 – REVISED FEBRUARY 2000
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
C0068 EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
C0068 I
off
Feature Supports Partial-Power-Down
Mode Operation
C0068 Supports 5-V V
CC
Operation
C0068 Package Options Include Plastic
Small-Outline Transistor (DBV, DCK)
Packages
description
This bus buffer gate is designed for 1.65-V to 5.5-V V
CC
operation.
The SN74LVC1G125 features a single line driver with a 3-state output. The output is disabled when the
output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74LVC1G125 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUT
OE A
Y
L H H
L LL
H X Z
logic symbol
†
EN
1
OE
2
A
Y
4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
AY
OE
1
24
PRODUCT PREVIEW
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PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
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change or discontinue these products without notice.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
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DBV OR DCK PACKAGE
(TOP VIEW)
1
2
3
5
4
OE
A
GND
V
CC
Y