1. General description
The 74AUP1G126 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G126 provides the single non-inverting buffer/line driver with 3-state output.
The 3-state output is controlled by the output enable input (OE). A LOW level at pin OE
causes the output to assume a high-impedance OFF-state.
This device has the input-disable feature, which allows floating input signals. The inputs
are disabled when the output enable input OE is LOW.
2. Features
a73 Wide supply voltage range from 0.8 V to 3.6 V
a73 High noise immunity
a73 Complies with JEDEC standards:
a78 JESD8-12 (0.8 V to 1.3 V)
a78 JESD8-11 (0.9 V to 1.65 V)
a78 JESD8-7 (1.2 V to 1.95 V)
a78 JESD8-5 (1.8 V to 2.7 V)
a78 JESD8-B (2.7 V to 3.6 V)
a73 ESD protection:
a78 HBM JESD22-A114-C exceeds 2000 V
a78 MM JESD22-A115-A exceeds 200 V
a78 CDM JESD22-C101-C exceeds 1000 V
a73 Low static power consumption; I
CC
= 0.9 µA (maximum)
a73 Latch-up performance exceeds 100 mA per JESD 78 Class II
a73 Inputs accept voltages up to 3.6 V
a73 Low noise overshoot and undershoot < 10 % of V
CC
a73 Input-disable feature allows floating input conditions
74AUP1G126
Low-power buffer/line driver; 3-state
Rev. 01 — 25 July 2005 Product data sheet