1/10February 2003
a73 HIGH SPEED :
t
PD
= 5.4 ns (MAX.) at V
CC
=3V
a73 5V TOLERANT INPUTS
a73 POWER DOWN PROTECTION ON INPUTS
a73 INPUT VOLTAGE LEVEL:
V
IL
=0.8V,V
IH
=2VatV
CC
=3V
a73 LOW POWER DISSIPATION:
I
CC
=4µA (MAX.) at T
A
=25°C
a73 LOW NOISE:
V
OLP
=0.3V(TYP.)atV
CC
=3.3V
a73 SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
|=I
OL
=4mA(MIN)atV
CC
=3V
a73 BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
a73 OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
a73 PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16373
a73 IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVX16373 is a low voltage CMOS 16 BIT
D-TYPE LATCH with 3 STATE OUTPUTS NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
These 16 bit D-TYPE latches are byte controlled
by two latch enable inputs (nLE) and two output
enable inputs(OE).
While the nLE input is held at a high level, the nQ
outputs will follow the data input precisely.
When the nLE is taken LOW, the nQ outputs will
be latched precisely at the logic level of D input
data.
While the (nOE) input is low, the nQoutputs will be
in a normal logic state (high or low logic level) and
while high levelthe outputs will be in a high imped-
ance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
74LVX16373
LOW VOLTAGE CMOS 16-BIT D-TYPE LATCH (3-STATE)
WITH 5V TOLERANT INPUTS
ORDER CODES
PACKAGE TUBE T & R
TSSOP 74LVX16373TTR
TSSOP
PIN CONNECTION