3.3V, 160-MHz, 1:10 Clock Distribution Buffer
B9946
Cypress Semiconductor Corporation • 3901 North First Street San Jose CA 95134 408-943-2600
Document #: 38-07077 Rev. *C Revised December 22, 2002
Product Features
• 160-MHz Clock Support
LVCMOS/LVTTL Compatible Inputs
10 Clock Outputs: Drive up to 20 Clock Lines
1X or 1/2X Configurable Outputs
Output Three-state Control
250 ps Maximum Output-to-Output Skew
Pin Compatible with MPC946
Industrial Temp. Range: –40°C to +85°C
32-Pin TQFP Package
Description
The B9946 is a low-voltage clock distribution buffer with the
capability to select one of two LVCMOS/LVTTL compatible in-
put clocks. These clock sources can be used to provide for test
clocks as well as the primary system clocks. All other control
inputs are LVCMOS/LVTTL compatible. The 10 outputs are
3.3V LVCMOS or LVTTL compatible and can drive two series
terminated 50Ω transmission lines. With this capability the
B9946 has an effective fanout of 1:20.
The B9946 is capable of generating 1X and 1/2X signals from
a 1X source. These signals are generated and retimed inter-
nally to ensure minimal skew between the 1X and 1/2X sig-
nals. SEL(A:C) inputs allow flexibility in selecting the ratio of
1X to1/2X outputs.
The B9946 outputs can also be three-stated via MR/OE# in-
put. When MR/OE# is set HIGH, it resets the internal flip-flops
and three-states the outputs.
B9946
MR
/O
E#
VSS QA
0
V
DDC
QA
1
VSS QA
2
V
DDC
V
DDC QC0
VSS QC1
V
DDC QC2
VSS QC3
VSS
QB0
VDDC
QB1
VSS
QB2
VDDC
VDDC
TCLK_SEL
VDD
TCLK0
TCLK1
DSELA
DSELB
DSELC
VSS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
3
QA0:2
3
QB0:2
4
QC0:3
0
1
0
1
0
1
0
1
/1
/2
R
TCLK0
TCLK_SEL
TCLK1
DSELA
DSELB
DSELC
MR/OE#
Block Diagram Pin Configuration