1/13September 2004
a73 5V TOLERANT INPUTS AND OUTPUTS
a73 HIGH SPEED:
t
PD
= 6.0 ns (MAX.) at V
CC
= 3V
a73 POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
a73 SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3V
a73 PCI BUS LEVELS GUARANTEED AT 24 mA
a73 BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
a73 OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
a73 PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 257
a73 LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
a73 ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LCX257 is a low voltage CMOS QUAD 2
CHANNEL MULTIPLEXER (3-STATE) fabricated
with sub-micron silicon gate and double-layer
metal wiring C
2
MOS technology. It is ideal for low
power and high speed 3.3V applications; it can be
interfaced to 5V signal environment for both inputs
and outputs.
It is composed of four independent 2 channel
multiplexers with common SELECT and ENABLE
(OE) INPUT. The 74LCX257 is a non-inverting
multiplexer. When the ENABLE INPUT is held
"High", all outputs become in high impedance
state. If SELECT INPUT is held "Low", "A" data is
selected, when SELECT INPUT is "High", "B" data
is chosen.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LCX257
LOW VOLTAGE CMOS QUAD 2 CHANNEL MULTIPLEXER
WITH 5V TOLERANT INPUTS AND OUTPUTS (3-STATE)

Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE T & R
SOP 74LCX257MTR
TSSOP 74LCX257TTR
TSSOPSOP
Rev. 4