5.8-GHz WDCT
Power Amplifier
ATR7035
Summary
Preliminary
Rev. 4577DS–DECT–11/04
Features
• Frequency Range 5 GHz to 6 GHz
P
OUT
Maximum 28 dBm
Gain Typically 19 dB
V
CC
3.0 V to 3.9 V
Package: QFN16
Current Consumption in Power Down Mode Typically ≤ 15 µA
Benefits
Biasing Control Extends Battery Life Time
Simple Input and Output Matching
One Single Supply Voltage Required
Electrostatic sensitive device.
Observe precautions for handling.
Description
Process
The 5-GHz power amplifier is designed using Atmel’s Silicon-Germanium (SiGe) pro-
cess and provides excellent noise performance as well as good power-added
efficiency.
Circuitry
The PA consists of a 2-stage amplifier with a maximum output power of 28 dBm. The
output stages were realized using an open-collector structure. The IC features 50-Ω
input matching. Power-up/down and output level are controlled at bias control pin 6
(V
CTL
).
Figure 1. Block Diagram
Matching
Bias control
RFIN
3
RFOUT
11
6
VCTL
16
VCC_CTL
VCC1
15
VCC2
13
ATR7035
RFOUT
10
Note: This is a summary document. A complete document
is available under NDA. For more information, please con-
tact your local Atmel sales office.