Ultra Low Power/High Speed CMOS SRAM
1M X 8 bit BH62UV8000BSI
R0201-BH62UV8000 Revision 1.0
Jul. 20051
n FEATURES
Wide VCC low operation voltage : 1.65V ~ 3.6V
Ultra low power consumption :
VCC = 3.0V Operation current : 5.0mA at 70ns at 25OC
1.5mA at 1MHz at 25OC
Standby current : 2.5uA at 25OC
VCC = 2.0V Data retention current : 2.5uA at 25OC
High speed access time :
-70 70ns at 1.8V at 85OC
Automatic power down when chip is deselected
Easy expansion with CE1, CE2 and OE options
Three state outputs and TTL compatible
Fully static operation, no clock, no refreash
Data retention supply voltage as low as 1.0V
n DESCRIPTION
The BH62UV8000 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 1,048,576 by 8 bits and
operates in a wide range of 1.65V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with typical operating current of 1.5mA at
1MHz at 3.6V/25OC and maximum access time of 70ns at 1.8V/85OC.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2) and active LOW output
enable (OE) and three-state output drivers.
The BH62UV8000 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BH62UV8000 is available in DICE form and 48-ball BGA package.

n PRODUCT FAMILY
POWER CONSUMPTION SPEED
(ns) STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
PRODUCT
FAMILY
OPERATING
TEMPERATURE
VCC
RANGE
VCC=1.8~3.6V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V
PKG TYPE
+0OC to +70OC 70 13uA 10uA 10mA 7mA
BH62UV8000AI

BH62UV8000DI
-25OC to +85OC
1.65V ~ 3.6V
70 15uA 12uA 10mA 7mA
BGA-48-0608

DICE


n PIN CONFIGURATIONS

























n BLOCK DIAGRAM

Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Detailed product characteristic test report is available upon request and being accepted.
G
H
F
E
D
C
B
A
1 2 3 4 5 6
A9 A11 A10 A19
A12
A14
A13
A15
WE
NC NC
NC
DQ7
A17
A16
A7
VSS
VCC
DQ2
DQ1
DQ6
DQ5
VSS
A5
OE
A3
A0
A6
A4
A1 A2 CE2
NC
NC NC
CE1
D04
NC
48-ball BGA top view
NC
NC
DQ0
VSS
VCC
D3
NC
A18
NC
A8
Address
Input
Buffer
Row
Decoder
Memory Array

1024 x 18192
Column I/O
Write Driver
Sense Amp
Column Decoder
Address Input Buffer
A15 A13 A16 A2 A1
Data
Input
Buffer
Control
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
8
8
8
8
10
1024
8192
1024 10
A17 A19
Data
Output
Buffer
A14
CE1
CE2
WE
OE
VCC
GND A0 A18